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| C8051F336/7/8/9 Mixed Signal ISP Flash MCU Family Analog Peripherals - 10-Bit ADC (`F336/8 only) * * * * * Up to 200 ksps Up to 20 external single-ended or differential inputs VREF from on-chip VREF, external pin or VDD Internal or external start of conversion source Built-in temperature sensor Memory - 768 bytes internal data RAM (256 + 512) - 16 kB Flash; In-system programmable in 512-byte Sectors (512 bytes are reserved) Digital Peripherals - 21 or 17 Port I/O; All 5 V tolerant with high sink current Pin-compatible with C8051F330 family of MCUs Hardware enhanced UART, SMBusTM (I2C compatible), and enhanced SPITM serial ports Four general purpose 16-bit counter/timers 16-Bit programmable counter array (PCA) with three capture/compare modules and enhanced PWM functionality Real time clock mode using timer and crystal - 10-Bit Current Output DAC (`F336/8 only) Comparator * * Programmable hysteresis and response time Configurable as interrupt or reset source On-Chip Debug - On-chip debug circuitry facilitates full speed, nonintrusive in-system debug (no emulator required) Provides breakpoints, single stepping, inspect/modify memory and registers Superior performance to emulation systems using ICE-chips, target pods, and sockets Low cost, complete development kit Supply Voltage 2.7 to 3.6 V - Built-in voltage supply monitor High-Speed 8051 C Core - Pipelined instruction architecture; executes 70% of Temperature Range: -40 to +85 C instructions in 1 or 2 system clocks Up to 25 MIPS throughput with 25 MHz clock Expanded interrupt handler Clock Sources - 24.5 MHz 2% Oscillator * * Supports crystal-less UART operation Low-power suspend mode with fast wake time - 80/20/40/10 kHz low-frequency, low-power oscillator External oscillator: Crystal, RC, C, or clock (1 or 2 pin modes) Can switch between clock sources on-the-fly; useful in power saving modes 20 or 24-Pin QFN (4 x 4 mm) ANALOG PERIPHERALS A M U X DIGITAL I/O UART SMBus SPI PCA Timer 0 Timer 1 Timer 2 Timer 3 CROSSBAR Port 0 Port 1 P2.0- P2.3* P2.4* *P2.1-2.4 QFN24 Only 10-bit 200 ksps ADC 10-bit Current DAC + TEMP SENSOR `F336/8 Only - VOLTAGE COMPARATOR 24.5 MHz PRECISION INTERNAL OSCILLATOR LOW FREQUENCY INTERNAL OSCILLATOR HIGH-SPEED CONTROLLER CORE 16 kB ISP FLASH FLEXIBLE INTERRUPTS 8051 CPU (25 MIPS) DEBUG CIRCUITRY 768 B SRAM POR WDT Rev. 0.2 8/07 Copyright (c) 2007 by Silicon Laboratories C8051F336/7/8/9 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. C8051F336/7/8/9 2 Rev. 0.2 C8051F336/7/8/9 Table of Contents 1. System Overview.................................................................................................... 16 1.1. CIP-51TM Microcontroller Core.......................................................................... 19 1.1.1. Fully 8051 Compatible.............................................................................. 19 1.1.2. Improved Throughput ............................................................................... 19 1.1.3. Additional Features .................................................................................. 19 1.2. On-Chip Memory............................................................................................... 20 1.3. On-Chip Debug Circuitry................................................................................... 21 1.4. Programmable Digital I/O and Crossbar ........................................................... 22 1.5. Serial Ports ....................................................................................................... 23 1.6. Programmable Counter Array ........................................................................... 23 1.7. 10-Bit Analog to Digital Converter..................................................................... 24 1.8. Comparator ....................................................................................................... 25 1.9. 10-bit Current Output DAC................................................................................ 26 2. Ordering Information.............................................................................................. 27 3. Pin Definitions ........................................................................................................ 28 4. QFN-20 Package Specifications............................................................................ 32 5. QFN-24 Package Specifications............................................................................ 33 6. Electrical Characteristics....................................................................................... 34 6.1. Absolute Maximum Specifications .................................................................... 34 6.2. Electrical Characteristics................................................................................... 35 7. 10-Bit ADC (ADC0, C8051F336/8 only) ................................................................. 43 7.1. Output Code Formatting ................................................................................... 44 7.2. Modes of Operation .......................................................................................... 44 7.2.1. Starting a Conversion............................................................................... 44 7.2.2. Tracking Modes........................................................................................ 45 7.2.3. Settling Time Requirements ..................................................................... 47 7.3. Programmable Window Detector ...................................................................... 51 7.3.1. Window Detector In Single-Ended Mode ................................................. 53 7.3.2. Window Detector In Differential Mode...................................................... 54 7.4. ADC0 Analog Multiplexer (C8051F336/8 only) ................................................. 55 8. Temperature Sensor (C8051F336/8 only) ............................................................. 58 9. 10-Bit Current Mode DAC (IDA0, C8051F336/8 only)........................................... 59 9.1. IDA0 Output Scheduling ................................................................................... 59 9.1.1. Update Output On-Demand ..................................................................... 59 9.1.2. Update Output Based on Timer Overflow ................................................ 60 9.1.3. Update Output Based on CNVSTR Edge................................................. 60 9.2. IDAC Output Mapping....................................................................................... 60 10. Voltage Reference (C8051F336/8 only)................................................................. 63 11. Comparator0 ........................................................................................................... 65 11.1.Comparator Multiplexer .................................................................................... 70 12. CIP-51 Microcontroller ........................................................................................... 72 12.1.Instruction Set................................................................................................... 73 12.1.1.Instruction and CPU Timing ..................................................................... 73 Rev. 0.2 3 C8051F336/7/8/9 12.2.CIP-51 Register Descriptions ........................................................................... 78 13. Memory Organization............................................................................................. 81 13.1.Program Memory.............................................................................................. 82 13.1.1.MOVX Instruction and Program Memory ................................................. 82 13.2.Data Memory .................................................................................................... 83 13.2.1.Internal RAM ............................................................................................ 83 13.2.1.1.General Purpose Registers ............................................................. 83 13.2.1.2.Bit Addressable Locations ............................................................... 83 13.2.1.3.Stack ............................................................................................ 84 13.2.2.External RAM ........................................................................................... 84 14. Special Function Registers ................................................................................... 85 15. Interrupts................................................................................................................. 89 15.1.MCU Interrupt Sources and Vectors................................................................. 90 15.1.1.Interrupt Priorities..................................................................................... 90 15.1.2.Interrupt Latency ...................................................................................... 90 15.2.Interrupt Register Descriptions ......................................................................... 91 15.3.External Interrupts /INT0 and /INT1.................................................................. 96 16. Flash Memory ......................................................................................................... 98 16.1.Programming The Flash Memory ..................................................................... 98 16.1.1.Flash Lock and Key Functions ................................................................. 98 16.1.2.Flash Erase Procedure ............................................................................ 98 16.1.3.Flash Write Procedure ............................................................................. 99 16.2.Non-volatile Data Storage ................................................................................ 99 16.3.Security Options ............................................................................................. 100 16.4.Flash Write and Erase Guidelines .................................................................. 102 16.4.1.VDD Maintenance and the VDD monitor ................................................. 102 16.4.2.PSWE Maintenance ............................................................................... 102 16.4.3.System Clock ......................................................................................... 103 17. Power Management Modes ................................................................................. 107 17.1.Idle Mode........................................................................................................ 107 17.2.Stop Mode ...................................................................................................... 108 17.3.Suspend Mode ............................................................................................... 108 18. Reset Sources....................................................................................................... 110 18.1.Power-On Reset ............................................................................................. 111 18.2.Power-Fail Reset / VDD Monitor .................................................................... 112 18.3.External Reset ................................................................................................ 113 18.4.Missing Clock Detector Reset ........................................................................ 113 18.5.Comparator0 Reset ........................................................................................ 114 18.6.PCA Watchdog Timer Reset .......................................................................... 114 18.7.Flash Error Reset ........................................................................................... 114 18.8.Software Reset ............................................................................................... 114 19. Oscillators and Clock Selection.......................................................................... 116 19.1.System Clock Selection.................................................................................. 117 19.2.Programmable Internal High-Frequency (H-F) Oscillator ............................... 118 19.2.1.Internal Oscillator Suspend Mode .......................................................... 118 4 Rev. 0.2 C8051F336/7/8/9 19.3.Programmable Internal Low-Frequency (L-F) Oscillator ................................ 120 19.3.1.Calibrating the Internal L-F Oscillator..................................................... 120 19.4.External Oscillator Drive Circuit...................................................................... 121 19.4.1.External Crystal Example....................................................................... 123 19.4.2.External RC Example............................................................................. 125 19.4.3.External Capacitor Example................................................................... 125 20. Port Input/Output.................................................................................................. 126 20.1.Port I/O Modes of Operation........................................................................... 127 20.1.1.Port Pins Configured for Analog I/O....................................................... 127 20.1.2.Port Pins Configured For Digital I/O....................................................... 128 20.1.3.Interfacing Port I/O to 5V Logic .............................................................. 128 20.2.Assigning Port I/O Pins to Analog and Digital Functions................................ 129 20.2.1.Assigning Port I/O Pins to Analog Functions ......................................... 129 20.2.2.Assigning Port I/O Pins to Digital Functions........................................... 130 20.2.3.Assigning Port I/O Pins to External Digital Event Capture Functions .... 130 20.3.Priority Crossbar Decoder .............................................................................. 131 20.4.Port I/O Initialization ....................................................................................... 133 20.5.Port Match ...................................................................................................... 136 20.6.Special Function Registers for Accessing and Configuring Port I/O .............. 138 21. SMBus ................................................................................................................... 145 21.1.Supporting Documents ................................................................................... 145 21.2.SMBus Configuration...................................................................................... 146 21.3.SMBus Operation ........................................................................................... 146 21.3.1.Transmitter Vs. Receiver........................................................................ 147 21.3.2.Arbitration............................................................................................... 147 21.3.3.Clock Low Extension.............................................................................. 148 21.3.4.SCL Low Timeout................................................................................... 148 21.3.5.SCL High (SMBus Free) Timeout .......................................................... 148 21.4.Using the SMBus............................................................................................ 148 21.4.1.SMBus Configuration Register............................................................... 149 21.4.2.SMB0CN Control Register ..................................................................... 152 21.4.2.1.Software ACK Generation ............................................................. 152 21.4.2.2.Hardware ACK Generation ............................................................ 152 21.4.3.Hardware Slave Address Recognition ................................................... 155 21.4.4.Data Register ......................................................................................... 157 21.5.SMBus Transfer Modes.................................................................................. 158 21.5.1.Write Sequence (Master) ....................................................................... 158 21.5.2.Read Sequence (Master) ....................................................................... 159 21.5.3.Write Sequence (Slave) ......................................................................... 160 21.5.4.Read Sequence (Slave) ......................................................................... 161 21.6.SMBus Status Decoding................................................................................. 161 22. UART0.................................................................................................................... 166 22.1.Enhanced Baud Rate Generation................................................................... 167 22.2.Operational Modes ......................................................................................... 168 Rev. 0.2 5 C8051F336/7/8/9 22.2.1.8-Bit UART ............................................................................................. 168 22.2.2.9-Bit UART ............................................................................................. 169 22.3.Multiprocessor Communications .................................................................... 169 23. Enhanced Serial Peripheral Interface (SPI0)...................................................... 174 23.1.Signal Descriptions......................................................................................... 175 23.1.1.Master Out, Slave In (MOSI).................................................................. 175 23.1.2.Master In, Slave Out (MISO).................................................................. 175 23.1.3.Serial Clock (SCK) ................................................................................. 175 23.1.4.Slave Select (NSS) ................................................................................ 175 23.2.SPI0 Master Mode Operation ......................................................................... 176 23.3.SPI0 Slave Mode Operation ........................................................................... 178 23.4.SPI0 Interrupt Sources ................................................................................... 178 23.5.Serial Clock Phase and Polarity ..................................................................... 179 23.6.SPI Special Function Registers ...................................................................... 180 24. Timers.................................................................................................................... 187 24.1.Timer 0 and Timer 1 ....................................................................................... 189 24.1.1.Mode 0: 13-bit Counter/Timer ................................................................ 189 24.1.2.Mode 1: 16-bit Counter/Timer ................................................................ 190 24.1.3.Mode 2: 8-bit Counter/Timer with Auto-Reload...................................... 191 24.1.4.Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................. 192 24.2.Timer 2 .......................................................................................................... 197 24.2.1.16-bit Timer with Auto-Reload................................................................ 197 24.2.2.8-bit Timers with Auto-Reload................................................................ 198 24.2.3.Low-Frequency Oscillator (LFO) Capture Mode .................................... 199 24.3.Timer 3 .......................................................................................................... 203 24.3.1.16-bit Timer with Auto-Reload................................................................ 203 24.3.2.8-bit Timers with Auto-Reload................................................................ 204 24.3.3.Low-Frequency Oscillator (LFO) Capture Mode .................................... 205 25. Programmable Counter Array ............................................................................. 209 25.1.PCA Counter/Timer ........................................................................................ 210 25.2.PCA0 Interrupt Sources.................................................................................. 211 25.3.Capture/Compare Modules ............................................................................ 212 25.3.1.Edge-triggered Capture Mode................................................................ 213 25.3.2.Software Timer (Compare) Mode........................................................... 214 25.3.3.High-Speed Output Mode ...................................................................... 215 25.3.4.Frequency Output Mode ........................................................................ 216 25.3.5. 8-bit, 9-bit, 10-bit and 11-bit Pulse Width Modulator Modes ................ 217 25.3.5.1. 8-bit Pulse Width Modulator Mode............................................... 217 25.3.5.2. 9/10/11-bit Pulse Width Modulator Mode..................................... 219 25.3.6. 16-Bit Pulse Width Modulator Mode..................................................... 220 25.4.Watchdog Timer Mode ................................................................................... 221 25.4.1.Watchdog Timer Operation .................................................................... 221 25.4.2.Watchdog Timer Usage ......................................................................... 222 25.5.Register Descriptions for PCA0...................................................................... 223 6 Rev. 0.2 C8051F336/7/8/9 26. C2 Interface ........................................................................................................... 229 26.1.C2 Interface Registers.................................................................................... 229 26.2.C2 Pin Sharing ............................................................................................... 232 Contact Information.................................................................................................. 234 Rev. 0.2 7 C8051F336/7/8/9 List of Figures 1. System Overview Figure 1.1. C8051F336/7 Block Diagram ................................................................. 17 Figure 1.2. C8051F338/9 Block Diagram ................................................................. 18 Figure 1.3. On-Chip Clock and Reset ...................................................................... 20 Figure 1.4. On-Chip Memory Map............................................................................ 21 Figure 1.5. Digital Crossbar Diagram ....................................................................... 22 Figure 1.6. PCA Block Diagram ............................................................................... 23 Figure 1.7. PCA Block Diagram ............................................................................... 23 Figure 1.8. 10-Bit ADC Block Diagram..................................................................... 24 Figure 1.9. Comparator0 Block Diagram.................................................................. 25 Figure 1.10. IDA0 Functional Block Diagram ........................................................... 26 2. Ordering Information 3. Pin Definitions Figure 3.1. QFN-20 Pinout Diagram (Top View) ...................................................... 30 Figure 3.2. QFN-24 Pinout Diagram (Top View) ...................................................... 31 4. QFN-20 Package Specifications Figure 4.1. QFN-20 Package Drawing ..................................................................... 32 5. QFN-24 Package Specifications Figure 5.1. QFN-24 Package Drawing ..................................................................... 33 6. Electrical Characteristics 7. 10-Bit ADC (ADC0, C8051F336/8 only) Figure 7.1. ADC0 Functional Block Diagram............................................................ 43 Figure 7.2. 10-Bit ADC Track and Conversion Example Timing .............................. 46 Figure 7.3. ADC0 Equivalent Input Circuits.............................................................. 47 Figure 7.4. ADC Window Compare Example: Right-Justified Single-Ended Data ... 53 Figure 7.5. ADC Window Compare Example: Left-Justified Single-Ended Data ..... 53 Figure 7.6. ADC Window Compare Example: Right-Justified Differential Data ....... 54 Figure 7.7. ADC Window Compare Example: Left-Justified Differential Data.......... 54 Figure 7.8. ADC0 Multiplexer Block Diagram........................................................... 55 8. Temperature Sensor (C8051F336/8 only) Figure 8.1. Temperature Sensor Transfer Function ................................................. 58 9. 10-Bit Current Mode DAC (IDA0, C8051F336/8 only) Figure 9.1. IDA0 Functional Block Diagram ............................................................. 59 Figure 9.2. IDA0 Data Word Mapping ...................................................................... 60 10. Voltage Reference (C8051F336/8 only) Figure 10.1. Voltage Reference Functional Block Diagram...................................... 63 11. Comparator0 Figure 11.1. Comparator0 Functional Block Diagram .............................................. 65 Figure 11.2. Comparator Hysteresis Plot ................................................................. 66 Figure 11.3. Comparator Input Multiplexer Block Diagram....................................... 70 12. CIP-51 Microcontroller Figure 12.1. CIP-51 Block Diagram.......................................................................... 72 8 Rev. 0.2 C8051F336/7/8/9 13. Memory Organization Figure 13.1. C8051F336/7/8/9 Memory Map............................................................ 81 Figure 13.2. Flash Program Memory Map................................................................ 82 14. Special Function Registers 15. Interrupts 16. Flash Memory Figure 16.1. Flash Program Memory Map.............................................................. 100 17. Power Management Modes 18. Reset Sources Figure 18.1. Reset Sources.................................................................................... 110 Figure 18.2. Power-On and VDD Monitor Reset Timing ........................................ 111 19. Oscillators and Clock Selection Figure 19.1. Oscillator Options ............................................................................... 116 Figure 19.2. External 32.768 kHz Quartz Crystal Oscillator Connection Diagram . 124 20. Port Input/Output Figure 20.1. Port I/O Functional Block Diagram ..................................................... 127 Figure 20.2. Port I/O Cell Block Diagram ............................................................... 128 Figure 20.3. Crossbar Priority Decoder with No Pins Skipped ............................... 131 Figure 20.4. Crossbar Priority Decoder with Crystal Pins Skipped ........................ 132 21. SMBus Figure 21.1. SMBus Block Diagram ....................................................................... 145 Figure 21.2. Typical SMBus Configuration ............................................................. 146 Figure 21.3. SMBus Transaction ............................................................................ 147 Figure 21.4. Typical SMBus SCL Generation......................................................... 150 Figure 21.5. Typical Master Write Sequence ......................................................... 158 Figure 21.6. Typical Master Read Sequence ......................................................... 159 Figure 21.7. Typical Slave Write Sequence ........................................................... 160 Figure 21.8. Typical Slave Read Sequence ........................................................... 161 22. UART0 Figure 22.1. UART0 Block Diagram ....................................................................... 166 Figure 22.2. UART0 Baud Rate Logic .................................................................... 167 Figure 22.3. UART Interconnect Diagram .............................................................. 168 Figure 22.4. 8-Bit UART Timing Diagram............................................................... 168 Figure 22.5. 9-Bit UART Timing Diagram............................................................... 169 Figure 22.6. UART Multi-Processor Mode Interconnect Diagram .......................... 170 23. Enhanced Serial Peripheral Interface (SPI0) Figure 23.1. SPI Block Diagram ............................................................................. 174 Figure 23.2. Multiple-Master Mode Connection Diagram ....................................... 177 Figure 23.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram 177 Figure 23.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram 177 Figure 23.5. Master Mode Data/Clock Timing ........................................................ 179 Figure 23.6. Slave Mode Data/Clock Timing (CKPHA = 0) .................................... 180 Figure 23.7. Slave Mode Data/Clock Timing (CKPHA = 1) .................................... 180 Rev. 0.2 9 C8051F336/7/8/9 Figure 23.8. SPI Master Timing (CKPHA = 0)........................................................ 184 Figure 23.9. SPI Master Timing (CKPHA = 1)........................................................ 184 Figure 23.10. SPI Slave Timing (CKPHA = 0)........................................................ 185 Figure 23.11. SPI Slave Timing (CKPHA = 1)........................................................ 185 24. Timers Figure 24.1. T0 Mode 0 Block Diagram.................................................................. 190 Figure 24.2. T0 Mode 2 Block Diagram.................................................................. 191 Figure 24.3. T0 Mode 3 Block Diagram.................................................................. 192 Figure 24.4. Timer 2 16-Bit Mode Block Diagram .................................................. 197 Figure 24.5. Timer 2 8-Bit Mode Block Diagram .................................................... 198 Figure 24.6. Timer 2 Low-Frequency Oscillation Capture Mode Block Diagram.... 199 Figure 24.7. Timer 3 16-Bit Mode Block Diagram .................................................. 203 Figure 24.8. Timer 3 8-Bit Mode Block Diagram .................................................... 204 Figure 24.9. Timer 3 Low-Frequency Oscillation Capture Mode Block Diagram.... 205 25. Programmable Counter Array Figure 25.1. PCA Block Diagram............................................................................ 209 Figure 25.2. PCA Counter/Timer Block Diagram.................................................... 210 Figure 25.3. PCA Interrupt Block Diagram ............................................................. 211 Figure 25.4. PCA Capture Mode Diagram.............................................................. 213 Figure 25.5. PCA Software Timer Mode Diagram .................................................. 214 Figure 25.6. PCA High-Speed Output Mode Diagram............................................ 215 Figure 25.7. PCA Frequency Output Mode ............................................................ 216 Figure 25.8. PCA 8-Bit PWM Mode Diagram ......................................................... 218 Figure 25.9. PCA 16-Bit PWM Mode...................................................................... 220 Figure 25.10. PCA Module 2 with Watchdog Timer Enabled ................................. 221 26. C2 Interface Figure 26.1. Typical C2 Pin Sharing....................................................................... 232 10 Rev. 0.2 C8051F336/7/8/9 List of Tables 1. System Overview 2. Ordering Information Table 2.1. Product Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3. Pin Definitions Table 3.1. Pin Definitions for the C8051F336/7/8/9 . . . . . . . . . . . . . . . . . . . . . . . . . 28 4. QFN-20 Package Specifications Table 4.1. QFN-20 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5. QFN-24 Package Specifications Table 5.1. QFN-24 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6. Electrical Characteristics Table 6.1. Absolute Maximum Ratings .................................................................... 34 Table 6.2. Global Electrical Characteristics ............................................................. 35 Table 6.3. Port I/O DC Electrical Characteristics ..................................................... 36 Table 6.4. Reset Electrical Characteristics .............................................................. 37 Table 6.5. Flash Electrical Characteristics ............................................................... 37 Table 6.6. Internal High-Frequency Oscillator Electrical Characteristics ................. 38 Table 6.7. Internal Low-Frequency Oscillator Electrical Characteristics .................. 38 Table 6.8. ADC0 Electrical Characteristics .............................................................. 39 Table 6.9. Temperature Sensor Electrical Characteristics ...................................... 40 Table 6.10. Voltage Reference Electrical Characteristics ........................................ 40 Table 6.11. IDAC Electrical Characteristics ............................................................. 41 Table 6.12. Comparator Electrical Characteristics .................................................. 42 7. 10-Bit ADC (ADC0, C8051F336/8 only) 8. Temperature Sensor (C8051F336/8 only) 9. 10-Bit Current Mode DAC (IDA0, C8051F336/8 only) 10. Voltage Reference (C8051F336/8 only) 11. Comparator0 12. CIP-51 Microcontroller Table 12.1. CIP-51 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 13. Memory Organization 14. Special Function Registers Table 14.1. Special Function Register (SFR) Memory Map . . . . . . . . . . . . . . . . . . 85 Table 14.2. Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 15. Interrupts Table 15.1. Interrupt Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 16. Flash Memory Table 16.1. Flash Security Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 17. Power Management Modes 18. Reset Sources 19. Oscillators and Clock Selection 20. Port Input/Output Table 20.1. Port I/O Assignment for Analog Functions . . . . . . . . . . . . . . . . . . . . . 129 Rev. 0.2 11 C8051F336/7/8/9 Table 20.2. Port I/O Assignment for Digital Functions . . . . . . . . . . . . . . . . . . . . . 130 Table 20.3. Port I/O Assignment for External Digital Event Capture Functions . . 130 21. SMBus Table 21.1. SMBus Clock Source Selection .......................................................... 149 Table 21.2. Minimum SDA Setup and Hold Times . . . . . . . . . . . . . . . . . . . . . . . . 150 Table 21.3. Sources for Hardware Changes to SMB0CN . . . . . . . . . . . . . . . . . . . 154 Table 21.4. Hardware Address Recognition Examples (EHACK = 1) . . . . . . . . . . 155 Table 21.5. SMBus Status Decoding With Hardware ACK Generation Disabled (EHACK = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Table 21.6. SMBus Status Decoding With Hardware ACK Generation Enabled (EHACK = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 22. UART0 Table 22.1. Timer Settings for Standard Baud Rates Using The Internal 24.5 MHz Oscillator . . . . . . . . . . . . . . . . . . . . . . . 173 Table 22.2. Timer Settings for Standard Baud Rates Using an External 22.1184 MHz Oscillator . . . . . . . . . . . . . . . . . . . . . 173 23. Enhanced Serial Peripheral Interface (SPI0) Table 23.1. SPI Slave Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 24. Timers 25. Programmable Counter Array Table 25.1. PCA Timebase Input Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Table 25.2. PCA0CPM and PCA0PWM Bit Settings for PCA Capture/Compare Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 Table 25.3. Watchdog Timer Timeout Intervals1 . . . . . . . . . . . . . . . . . . . . . . . . . 222 26. C2 Interface 12 Rev. 0.2 C8051F336/7/8/9 List of Registers SFR Definition 7.1. ADC0CF: ADC0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 SFR Definition 7.2. ADC0H: ADC0 Data Word MSB . . . . . . . . . . . . . . . . . . . . . . . . . . 49 SFR Definition 7.3. ADC0L: ADC0 Data Word LSB . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 SFR Definition 7.4. ADC0CN: ADC0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 SFR Definition 7.5. ADC0GTH: ADC0 Greater-Than Data High Byte . . . . . . . . . . . . . 51 SFR Definition 7.6. ADC0GTL: ADC0 Greater-Than Data Low Byte . . . . . . . . . . . . . . 51 SFR Definition 7.7. ADC0LTH: ADC0 Less-Than Data High Byte . . . . . . . . . . . . . . . . 52 SFR Definition 7.8. ADC0LTL: ADC0 Less-Than Data Low Byte . . . . . . . . . . . . . . . . . 52 SFR Definition 7.9. AMX0P: AMUX0 Positive Channel Select . . . . . . . . . . . . . . . . . . . 56 SFR Definition 7.10. AMX0N: AMUX0 Negative Channel Select . . . . . . . . . . . . . . . . . 57 SFR Definition 9.1. IDA0CN: IDA0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 SFR Definition 9.2. IDA0H: IDA0 Data Word MSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 SFR Definition 9.3. IDA0L: IDA0 Data Word LSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 SFR Definition 10.1. REF0CN: Reference Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 SFR Definition 11.1. CPT0CN: Comparator0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . 68 SFR Definition 11.2. CPT0MD: Comparator0 Mode Selection . . . . . . . . . . . . . . . . . . . 69 SFR Definition 11.3. CPT0MX: Comparator0 MUX Selection . . . . . . . . . . . . . . . . . . . 71 SFR Definition 12.1. DPL: Data Pointer Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 SFR Definition 12.2. DPH: Data Pointer High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 SFR Definition 12.3. SP: Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 SFR Definition 12.4. ACC: Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 SFR Definition 12.5. B: B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 SFR Definition 12.6. PSW: Program Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 SFR Definition 13.1. EMI0CN: External Memory Interface Control . . . . . . . . . . . . . . . 84 SFR Definition 15.1. IE: Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 SFR Definition 15.2. IP: Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 SFR Definition 15.3. EIE1: Extended Interrupt Enable 1 . . . . . . . . . . . . . . . . . . . . . . . 94 SFR Definition 15.4. EIP1: Extended Interrupt Priority 1 . . . . . . . . . . . . . . . . . . . . . . . 95 SFR Definition 15.5. IT01CF: INT0/INT1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . 97 SFR Definition 16.1. PSCTL: Program Store R/W Control . . . . . . . . . . . . . . . . . . . . . 104 SFR Definition 16.2. FLKEY: Flash Lock and Key . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 SFR Definition 16.3. FLSCL: Flash Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 SFR Definition 17.1. PCON: Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 SFR Definition 18.1. VDM0CN: VDD Monitor Control . . . . . . . . . . . . . . . . . . . . . . . . 113 SFR Definition 18.2. RSTSRC: Reset Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 SFR Definition 19.1. CLKSEL: Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 SFR Definition 19.2. OSCICL: Internal H-F Oscillator Calibration . . . . . . . . . . . . . . . 118 SFR Definition 19.3. OSCICN: Internal H-F Oscillator Control . . . . . . . . . . . . . . . . . . 119 SFR Definition 19.4. OSCLCN: Internal L-F Oscillator Control . . . . . . . . . . . . . . . . . . 120 SFR Definition 19.5. OSCXCN: External Oscillator Control . . . . . . . . . . . . . . . . . . . . 122 SFR Definition 20.1. XBR0: Port I/O Crossbar Register 0 . . . . . . . . . . . . . . . . . . . . . 134 SFR Definition 20.2. XBR1: Port I/O Crossbar Register 1 . . . . . . . . . . . . . . . . . . . . . 135 SFR Definition 20.3. P0MASK: Port 0 Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . 136 Rev. 0.2 13 C8051F336/7/8/9 SFR Definition 20.4. P0MAT: Port 0 Match Register . . . . . . . . . . . . . . . . . . . . . . . . . 136 SFR Definition 20.5. P1MASK: Port 1 Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . 137 SFR Definition 20.6. P1MAT: Port 1 Match Register . . . . . . . . . . . . . . . . . . . . . . . . . 137 SFR Definition 20.7. P0: Port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 SFR Definition 20.8. P0MDIN: Port 0 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 SFR Definition 20.9. P0MDOUT: Port 0 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 139 SFR Definition 20.10. P0SKIP: Port 0 Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 SFR Definition 20.11. P1: Port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 SFR Definition 20.12. P1MDIN: Port 1 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 SFR Definition 20.13. P1MDOUT: Port 1 Output Mode . . . . . . . . . . . . . . . . . . . . . . . 141 SFR Definition 20.14. P1SKIP: Port 1 Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 SFR Definition 20.15. P2: Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 SFR Definition 20.16. P2MDIN: Port 2 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 SFR Definition 20.17. P2MDOUT: Port 2 Output Mode . . . . . . . . . . . . . . . . . . . . . . . 143 SFR Definition 20.18. P2SKIP: Port 2 Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 SFR Definition 21.1. SMB0CF: SMBus Clock/Configuration . . . . . . . . . . . . . . . . . . . 151 SFR Definition 21.2. SMB0CN: SMBus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 SFR Definition 21.3. SMB0ADR: SMBus Slave Address . . . . . . . . . . . . . . . . . . . . . . 156 SFR Definition 21.4. SMB0ADM: SMBus Slave Address Mask . . . . . . . . . . . . . . . . . 156 SFR Definition 21.5. SMB0DAT: SMBus Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 SFR Definition 22.1. SCON0: Serial Port 0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . 171 SFR Definition 22.2. SBUF0: Serial (UART0) Port Data Buffer . . . . . . . . . . . . . . . . . 172 SFR Definition 23.1. SPI0CFG: SPI0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 181 SFR Definition 23.2. SPI0CN: SPI0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 SFR Definition 23.3. SPI0CKR: SPI0 Clock Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 SFR Definition 23.4. SPI0DAT: SPI0 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 SFR Definition 24.1. CKCON: Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 SFR Definition 24.2. TCON: Timer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 SFR Definition 24.3. TMOD: Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 SFR Definition 24.4. TL0: Timer 0 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 SFR Definition 24.5. TL1: Timer 1 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 SFR Definition 24.6. TH0: Timer 0 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 SFR Definition 24.7. TH1: Timer 1 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 SFR Definition 24.8. TMR2CN: Timer 2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 SFR Definition 24.9. TMR2RLL: Timer 2 Reload Register Low Byte . . . . . . . . . . . . . 201 SFR Definition 24.10. TMR2RLH: Timer 2 Reload Register High Byte . . . . . . . . . . . 201 SFR Definition 24.11. TMR2L: Timer 2 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 SFR Definition 24.12. TMR2H Timer 2 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 SFR Definition 24.13. TMR3CN: Timer 3 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 SFR Definition 24.14. TMR3RLL: Timer 3 Reload Register Low Byte . . . . . . . . . . . . 207 SFR Definition 24.15. TMR3RLH: Timer 3 Reload Register High Byte . . . . . . . . . . . 207 SFR Definition 24.16. TMR3L: Timer 3 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 SFR Definition 24.17. TMR3H Timer 3 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 SFR Definition 25.1. PCA0CN: PCA Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 SFR Definition 25.2. PCA0MD: PCA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 14 Rev. 0.2 C8051F336/7/8/9 SFR Definition 25.3. PCA0PWM: PCA PWM Configuration . . . . . . . . . . . . . . . . . . . . 225 SFR Definition 25.4. PCA0CPMn: PCA Capture/Compare Mode . . . . . . . . . . . . . . . 226 SFR Definition 25.5. PCA0L: PCA Counter/Timer Low Byte . . . . . . . . . . . . . . . . . . . 227 SFR Definition 25.6. PCA0H: PCA Counter/Timer High Byte . . . . . . . . . . . . . . . . . . . 227 SFR Definition 25.7. PCA0CPLn: PCA Capture Module Low Byte . . . . . . . . . . . . . . . 228 SFR Definition 25.8. PCA0CPHn: PCA Capture Module High Byte . . . . . . . . . . . . . . 228 C2 Register Definition 26.1. C2ADD: C2 Address . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 C2 Register Definition 26.2. DEVICEID: C2 Device ID . . . . . . . . . . . . . . . . . . . . . . . . 230 C2 Register Definition 26.3. REVID: C2 Revision ID . . . . . . . . . . . . . . . . . . . . . . . . . 230 C2 Register Definition 26.4. FPCTL: C2 Flash Programming Control . . . . . . . . . . . . 231 C2 Register Definition 26.5. FPDAT: C2 Flash Programming Data . . . . . . . . . . . . . . 231 Rev. 0.2 15 C8051F336/7/8/9 1. System Overview C8051F336/7/8/9 devices are fully integrated mixed-signal System-on-a-Chip MCUs. Highlighted features are listed below. Refer to Table 2.1 for specific product feature selection and part ordering numbers. * * * * * * * * * * * * * * * High-speed pipelined 8051-compatible microcontroller core (up to 25 MIPS) In-system, full-speed, non-intrusive debug interface (on-chip) True 10-bit 200 ksps 20-channel single-ended/differential ADC with analog multiplexer 10-bit Current Output DAC Precision programmable 24.5 MHz internal oscillator Low-power, low-frequency oscillator 16 kB of on-chip Flash memory--512 bytes are reserved 768 bytes of on-chip RAM SMBus/I2C, Enhanced UART, and Enhanced SPI serial interfaces implemented in hardware Four general-purpose 16-bit timers Programmable Counter/Timer Array (PCA) with three capture/compare modules and Watchdog Timer function On-chip Power-On Reset, VDD Monitor, and Temperature Sensor On-chip Voltage Comparator 21 or 17 Port I/O (5 V tolerant) Low-power suspend mode with fast wake-up time With on-chip Power-On Reset, VDD monitor, Watchdog Timer, and clock oscillator, the C8051F336/7/8/9 devices are truly stand-alone System-on-a-Chip solutions. The Flash memory can be reprogrammed even in-circuit, providing non-volatile data storage, and also allowing field upgrades of the 8051 firmware. User software has complete control of all peripherals, and may individually shut down any or all peripherals for power savings. The on-chip Silicon Labs 2-Wire (C2) Development Interface allows non-intrusive (uses no on-chip resources), full speed, in-circuit debugging using the production MCU installed in the final application. This debug logic supports inspection and modification of memory and registers, setting breakpoints, single stepping, run and halt commands. All analog and digital peripherals are fully functional while debugging using C2. The two C2 interface pins can be shared with user functions, allowing in-system debugging without occupying package pins. Each device is specified for 2.7 to 3.6 V operation over the industrial temperature range (-40 to +85 C). The Port I/O and RST pins are tolerant of input signals up to 5 V. The C8051F336/7 are available in a 20pin QFN package and the C8051F338/9 are available in a 24-pin QFN package. Both package options are lead-free and RoHS compliant. See Table 2.1 for ordering information. Block diagrams are included in Figure 1.1 and Figure 1.2. 16 Rev. 0.2 C8051F336/7/8/9 Power On Reset Reset CIP-51 8051 Controller Core 16k Byte ISP Flash Program Memory 256 Byte SRAM Port I/O Configuration Digital Peripherals UART Timers 0, 1, 2, 3 PCA/ WDT SMBus Priority Crossbar Decoder Port 0 Drivers C2CK/RST Debug / Programming Hardware C2D P0.0/VREF P0.1/IDA0 P0.2/XTAL1 P0.3/XTAL2 P0.4/TX P0.5/RX P0.6/CNVSTR P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0/C2D 512 Byte XRAM VDD GND Power Net SYSCLK SPI Crossbar Control Port 1 Drivers SFR Bus Precision 24.5 MHz Oscillator Low-Freq. Oscillator XTAL1 XTAL2 External Oscillator Circuit Analog Peripherals 10-bit IDAC VDD VREF VDD VREF Temp Sensor GND + - IDA0 Port 2 Drivers 10-bit 200 ksps ADC C8051F336 Only CP0, CP0A A M U X System Clock Configuration Comparator Figure 1.1. C8051F336/7 Block Diagram Rev. 0.2 17 C8051F336/7/8/9 Power On Reset Reset CIP-51 8051 Controller Core 16 kB ISP Flash Program Memory 256 Byte SRAM Port I/O Configuration Digital Peripherals UART Timers 0, 1, 2, 3 PCA/ WDT SMBus Priority Crossbar Decoder Port 0 Drivers C2CK/RST Debug / Programming Hardware C2D P0.0/VREF P0.1/IDA0 P0.2/XTAL1 P0.3/XTAL2 P0.4/TX P0.5/RX P0.6/CNVSTR P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4/C2D 512 Byte XRAM VDD GND Power Net SYSCLK SPI Crossbar Control Port 1 Drivers SFR Bus Precision 24.5 MHz Oscillator Low-Freq. Oscillator XTAL1 XTAL2 External Oscillator Circuit Analog Peripherals 10-bit IDAC VDD VREF VDD VREF Temp Sensor GND + - IDA0 Port 2 Drivers 10-bit 200 ksps ADC C8051F338 Only CP0, CP0A A M U X System Clock Configuration Comparator Figure 1.2. C8051F338/9 Block Diagram 18 Rev. 0.2 C8051F336/7/8/9 1.1. CIP-51TM Microcontroller Core 1.1.1. Fully 8051 Compatible The C8051F336/7/8/9 family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP-51 is fully compatible with the MCS-51TM instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The CIP-51 core offers all the peripherals included with a standard 8052, including four 16-bit counter/timers, a full-duplex UART with extended baud rate configuration, an enhanced SPI port, 768 bytes of internal RAM, 128 byte Special Function Register (SFR) address space, and 17 or 21 I/O pins. 1.1.2. Improved Throughput The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to execute with a maximum system clock of 12-to-24 MHz. By contrast, the CIP-51 core executes 70% of its instructions in one or two system clock cycles, with only four instructions taking more than four system clock cycles. The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that require each execution time. Clocks to Execute Number of Instructions 1 26 2 50 2/3 5 3 14 3/4 7 4 3 4/5 1 5 2 8 1 With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. 1.1.3. Additional Features The C8051F336/7/8/9 SoC family includes several key enhancements to the CIP-51 core and peripherals to improve performance and ease of use in end applications. The extended interrupt handler provides multiple interrupt sources into the CIP-51 allowing numerous analog and digital peripherals to interrupt the controller. An interrupt driven system requires less intervention by the MCU, giving it more effective throughput. The extra interrupt sources are very useful when building multi-tasking, real-time systems. Eight reset sources are available: power-on reset circuitry (POR), an on-chip VDD monitor (forces reset when power supply voltage drops below safe levels), a Watchdog Timer, a Missing Clock Detector, a voltage level detection from Comparator0, a forced software reset, an external reset pin, and an illegal Flash access protection circuit. Each reset source except for the POR, Reset Input Pin, or Flash error may be disabled by the user in software. The WDT may be permanently enabled in software after a power-on reset during MCU initialization. The internal oscillator is factory calibrated to 24.5 MHz and is accurate to 2% over the full temperature and supply range. The internal oscillator period can also be adjusted by user firmware. An additional lowfrequency oscillator is also available which facilitates low-power operation. An external oscillator drive circuit is included, allowing an external crystal, ceramic resonator, capacitor, RC, or CMOS clock source to generate the system clock. If desired, the system clock source may be switched on-the-fly between both internal and external oscillator circuits. An external oscillator can also be extremely useful in low power applications, allowing the MCU to run from a slow (power saving) source, while periodically switching to the fast (up to 25 MHz) internal oscillator as needed. Rev. 0.2 19 C8051F336/7/8/9 VDD Power On Reset Supply Monitor Px.x Px.x Comparator 0 + C0RSEF + - Enable '0' (wired-OR) /RST Missing Clock Detector (oneshot) EN Reset Funnel PCA WDT (Software Reset) SWRSF EN Low Frequency Oscillator Internal Oscillator System Clock MCD Enable XTAL1 XTAL2 External Oscillator Drive Clock Select CIP-51 Microcontroller Core Extended Interrupt Handler WDT Enable Errant FLASH Operation System Reset Figure 1.3. On-Chip Clock and Reset 1.2. On-Chip Memory The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data RAM, with the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general purpose RAM, and direct addressing accesses the 128 byte SFR address space. The lower 128 bytes of RAM are accessible via direct and indirect addressing. The first 32 bytes are addressable as four banks of general purpose registers, and the next 16 bytes can be byte addressable or bit addressable. Program memory consists of 16 kB of Flash. This memory may be reprogrammed in-system in 512 byte sectors, and requires no special off-chip programming voltage. See Figure 1.4 for the MCU system memory map. 20 Rev. 0.2 C8051F336/7/8/9 PROGRAM/DATA MEMORY (FLASH) 0xFF 0x3E00 0x3DFF RESERVED 0x80 0x7F 16 kB FLASH (In-System Programmable in 512 Byte Sectors) 0x30 0x2F 0x20 0x1F 0x00 0x0000 DATA MEMORY (RAM) INTERNAL DATA ADDRESS SPACE Upper 128 RAM (Indirect Addressing Only) (Direct and Indirect Addressing) Bit Addressable General Purpose Registers Special Function Register's (Direct Addressing Only) Lower 128 RAM (Direct and Indirect Addressing) EXTERNAL DATA ADDRESS SPACE 0xFFFF Same 512 bytes as from 0x0000 to 0x01FF, wrapped on 512-byte boundaries 0x0200 0x01FF 0x0000 XRAM - 512 Bytes (accessable using MOVX instruction) Figure 1.4. On-Chip Memory Map 1.3. On-Chip Debug Circuitry The C8051F336/7/8/9 devices include on-chip Silicon Labs 2-Wire (C2) debug circuitry that provides nonintrusive, full speed, in-circuit debugging of the production part installed in the end application. Silicon Labs' debugging system supports inspection and modification of memory and registers, breakpoints, and single stepping. No additional target RAM, program memory, timers, or communications channels are required. All the digital and analog peripherals are functional and work correctly while debugging. All the peripherals (except for the ADC and SMBus) are stalled when the MCU is halted, during single stepping, or at a breakpoint in order to keep them synchronized. The C8051F336DK development kit provides all the hardware and software necessary to develop application code and perform in-circuit debugging with the C8051F336/7/8/9 MCUs. The kit includes software with a developer's studio and debugger, evaluation compiler and assembler, and a debug adapter. It also has a target application board with the associated MCU installed and prototyping area, plus the required cables, and power supply. The IDE software requires a PC running a Windows operating system. The Silicon Labs IDE interface is a vastly superior developing and debugging configuration, compared to standard MCU emulators that use on-board "ICE Chips" and require the MCU in the application board to Rev. 0.2 21 C8051F336/7/8/9 be socketed. Silicon Labs' debug paradigm increases ease of use and preserves the performance of the precision analog peripherals. 1.4. Programmable Digital I/O and Crossbar C8051F338/9 devices include 21 I/O pins (two byte-wide Ports and one 5-bit-wide Port). C8051F336/7 devices include 17 I/O pins (two byte-wide Ports and one 5-bit-wide Port). The C8051F336/7/8/9 Ports behave like typical 8051 Ports with a few enhancements. Each Port pin may be configured as an analog input or a digital I/O pin. Pins selected as digital I/Os may additionally be configured for push-pull or opendrain output. The "weak pullups" that are fixed on typical 8051 devices may be globally disabled, providing power saving capabilities. The Digital Crossbar allows mapping of internal digital system resources to Port I/O pins. (See Figure 1.5.) On-chip counter/timers, serial buses, HW interrupts, comparator output, and other digital signals in the controller can be configured to appear on the Port I/O pins specified in the Crossbar Control registers. This allows the user to select the exact mix of general purpose Port I/O and digital resources needed for the particular application. XBR0, XBR1, PnSKIP Registers PnMDOUT, PnMDIN Registers Priority Decoder Highest Priority (Internal Digital Signals) UART SPI SMBus CP0 Outputs SYSCLK 2 4 2 2 8 P0 I/O Cells P0.0 P0.7 P1.0 P1.7 P2.0 P2.3* Digital Crossbar 8 P1 I/O Cells 4 P2 I/O Cells PCA Lowest Priority T0, T1 4 2 8 (Port Latches) P0 (P0.0-P0.7) 8 *P2.1-P2.3 only available on QFN24 Packages P1 (P1.0-P1.7) 4 P2 (P2.0-P2.3*) Figure 1.5. Digital Crossbar Diagram 22 Rev. 0.2 C8051F336/7/8/9 1.5. Serial Ports The C8051F336/7/8/9 Family includes an SMBus/I2C interface, a full-duplex UART with enhanced baud rate configuration, and an Enhanced SPI interface. Each of the serial buses is fully implemented in hardware and makes extensive use of the CIP-51's interrupts, thus requiring very little CPU intervention. 1.6. Programmable Counter Array An on-chip Programmable Counter/Timer Array (PCA) is included in addition to the four 16-bit general purpose counter/timers. The PCA consists of a dedicated 16-bit counter/timer time base with three programmable capture/compare modules. The PCA clock is derived from one of six sources: the system clock divided by 12, the system clock divided by 4, Timer 0 overflows, an External Clock Input (ECI), the system clock, or the external oscillator clock source divided by 8. The external clock source selection is useful for real-time clock functionality, where the PCA is clocked by an external source while the internal oscillator drives the system clock. Each capture/compare module can be configured to operate in a variety of modes: Edge-Triggered Capture, Software Timer, High Speed Output, Pulse Width Modulator (8, 9, 10, 11, or 16-bit), or Frequency Output. Additionally, Capture/Compare Module 2 offers watchdog timer (WDT) capabilities. Following a system reset, Module 2 is configured and enabled in WDT mode. The PCA Capture/Compare Module I/O and External Clock Input may be routed to Port I/O via the Digital Crossbar. SYSCLK/12 SYSCLK/4 Timer 0 Overflow ECI SYSCLK External Clock/8 PCA CLOCK MUX 16-Bit Counter/Timer Capture/Compare Module 0 Capture/Compare Module 1 Capture/Compare Module 2 CEX0 CEX2 CEX1 ECI Digital Crossbar Port I/O Figure 1.7. PCA Block Diagram Rev. 0.2 23 C8051F336/7/8/9 1.7. 10-Bit Analog to Digital Converter The C8051F336/8 devices include an on-chip 10-bit SAR ADC with a differential input multiplexer. With a maximum throughput of 200 ksps, the ADC offers true 10-bit linearity with an INL and DNL of 1 LSB. The ADC system includes a configurable analog multiplexer that selects both positive and negative ADC inputs. Up to twenty port I/O pins are available as an ADC inputs; additionally, the on-chip Temperature Sensor output and the power supply voltage (VDD) are available as ADC inputs. User firmware may shut down the ADC to save power. Conversions can be started in six ways: a software command, an overflow of Timer 0, 1, 2, or 3, or an external convert start signal. This flexibility allows the start of conversion to be triggered by software events, a periodic signal (timer overflows), or external HW signals. Conversion completions are indicated by a status bit and an interrupt (if enabled). The resulting 10-bit data word is latched into the ADC data SFRs upon completion of a conversion. Window compare registers for the ADC data can be configured to interrupt the controller when ADC data is either within or outside of a specified range. The ADC can monitor a key voltage continuously in background mode, but not interrupt the controller unless the converted data is within/outside the specified range. Analog Multiplexer P0.0 Configuration, Control, and Data Registers AMUX P2.3 Temp Sensor Start Conversion 000 001 010 011 100 101 AD0BUSY (W) Timer 0 Overflow Timer 2 Overflow Timer 1 Overflow CNVSTR Input Timer 3 Overflow VDD P0.0 (+) 10-Bit SAR (-) AMUX P2.3 VREF GND ADC End of Conversion Interrupt 16 ADC Data Registers Window Compare Logic Window Compare Interrupt Figure 1.8. 10-Bit ADC Block Diagram 24 Rev. 0.2 C8051F336/7/8/9 1.8. Comparator C8051F336/7/8/9 devices include an on-chip voltage comparator that is enabled/disabled and configured via user software. Port I/O pins may be configured as comparator inputs via a selection mux. Two comparator outputs may be routed to a Port pin if desired: a latched output and/or an unlatched (asynchronous) output. Comparator response time is programmable, allowing the user to select between high-speed and low-power modes. Positive and negative hysteresis are also configurable. Comparator interrupts may be generated on rising, falling, or both edges. When in IDLE mode, these interrupts may be used as a "wake-up" source. Comparator0 may also be configured as a reset source. Figure 1.9 shows the Comparator0 block diagram. CPT0MX CMX0N0 CMX0N1 CMX0N2 CMX0N3 CMX0P0 P0.0 P0.2 P0.4 P0.6 P1.0 P1.2 P1.4 P1.6 P2.0 P2.2 P0.1 P0.3 P0.5 P0.7 P1.1 P1.3 P1.5 P1.7 P2.1 P2.3 CMX0P1 CMX0P2 CMX0P3 CPT0CN CP0HYN0 CP0HYN1 CP0HYP0 CP0HYP1 CP0OUT CP0RIF CP0FIF CP0EN VDD CP0 + + CP0 D SET CP0 Q D SET Q GND CLR Q CLR Q Crossbar (SYNCHRONIZER) CP0A Reset Decision Tree CP0 Interrupt CPT0MD CP0MD0 CP0MD1 CP0RIE CP0FIE CP0RIF CP0FIF 0 1 0 1 CP0EN 0 1 EA 0 1 Figure 1.9. Comparator0 Block Diagram Rev. 0.2 25 C8051F336/7/8/9 1.9. 10-bit Current Output DAC The C8051F336/8 devices include a 10-bit current-mode Digital-to-Analog Converter (IDA0). The maximum current output of the IDA0 can be adjusted for three different current settings; 0.5 mA, 1 mA, and 2 mA. IDA0 features a flexible output update mechanism which allows for seamless full-scale changes and supports jitter-free updates for waveform generation. Three update modes are provided, allowing IDA0 output updates on a write to IDA0H, on a Timer overflow, or on an external pin edge. Timer 0 Timer 1 Timer 2 Timer 3 10 IDA0H IDA0CN IDA0EN IDA0CM2 IDA0CM1 IDA0CM0 IDA0OMD1 IDA0OMD0 IDA0H 8 Latch IDA0 IDA0 IDA0L 2 Figure 1.10. IDA0 Functional Block Diagram 26 Rev. 0.2 CNVSTR 2. Ordering Part Number MIPS (Peak) Flash Memory (kB) RAM (bytes) Calibrated Internal 24.5 MHz Oscillator Internal 80 kHz Oscillator SMBus/I2C Enhanced SPI UART C8051F339-GM 25 16 768 C8051F338-GM 25 16 768 C8051F337-GM 25 16 768 C8051F336-GM 25 16 768 Ordering Information 4 4 4 4 Table 2.1. Product Selection Guide Rev. 0.2 Timers (16-bit) RTC OPeration Programmable Counter Array 21 QFN-24 17 Digital Port I/Os 10-bit 200ksps ADC 10-bit Current Output DAC Internal Voltage Reference Temperature Sensor Analog Comparator Lead-free (RoHS Compliant) 21 -- -- -- -- QFN-24 17 -- -- -- -- QFN-20 C8051F336/7/8/9 QFN-20 Package 27 C8051F336/7/8/9 3. Pin Definitions Table 3.1. Pin Definitions for the C8051F336/7/8/9 Name VDD GND Pin `F336/7 3 2 Pin `F338/9 4 3 Type Power Supply Voltage. Ground. Note: This ground connection is required. The center pad may optionally be connected to ground also. Description RST/ 4 5 D I/O Device Reset. Open-drain output of internal POR or VDD monitor. An external source can initiate a system reset by driving this pin low for at least 10 s. Clock signal for the C2 Debug Interface. Port 2.0. Bi-directional data signal for the C2 Debug Interface. Port 2.4. Bi-directional data signal for the C2 Debug Interface. C2CK P2.0/ C2D P2.4/ C2D P0.0/ 1 2 6 5 D I/O D I/O D I/O D I/O D I/O D I/O or Port 0.0. A In A In External VREF input. VREF P0.1 20 1 D I/O or Port 0.1. A In AOut IDA0 Output. IDA0 P0.2/ 19 24 D I/O or Port 0.2. A In A In External Clock Input. This pin is the external oscillator return for a crystal or resonator. XTAL1 P0.3/ 18 23 D I/O or Port 0.3. A In XTAL2 A I/O or External Clock Output. For an external crystal or resonator, this pin is the excitation driver. This pin is the external clock D In input for CMOS, capacitor, or RC oscillator configurations. 17 22 D I/O or Port 0.4. A In P0.4 28 Rev. 0.2 C8051F336/7/8/9 Table 3.1. Pin Definitions for the C8051F336/7/8/9 (Continued) Name P0.5 P0.6/ Pin `F336/7 16 15 Pin `F338/9 21 20 Type D I/O or Port 0.5. A In D I/O or Port 0.6. A In D In 14 13 12 11 10 9 8 7 6 5 19 18 17 16 15 14 13 12 11 10 9 8 7 ADC0 External Convert Start or IDA0 Update Source Input. Description CNVSTR P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 D I/O or Port 0.7. A In D I/O or Port 1.0. A In D I/O or Port 1.1. A In D I/O or Port 1.2. A In D I/O or Port 1.3. A In D I/O or Port 1.4. A In D I/O or Port 1.5. A In D I/O or Port 1.6. A In D I/O or Port 1.7. A In D I/O or Port 2.0. A In D I/O or Port 2.1. A In D I/O or Port 2.2. A In D I/O or Port 2.3. A In Rev. 0.2 29 C8051F336/7/8/9 P0.1 P0.2 P0.3 P0.4 17 P0.5 16 20 19 P0.0 GND VDD /RST/C2CK P2.0/C2D 1 2 3 4 5 GND (optional) 18 15 14 P0.6 P0.7 P1.0 P1.1 P1.2 C8051F336/7 Top View 13 12 11 P1.7 P1.6 P1.5 P1.4 Figure 3.1. QFN-20 Pinout Diagram (Top View) 30 Rev. 0.2 P1.3 10 6 7 8 9 C8051F336/7/8/9 P0.2 P0.3 P0.4 P0.5 P0.6 20 P0.7 19 24 23 22 21 P0.1 P0.0 GND VDD /RST/C2CK P2.4/C2D 1 2 3 4 5 GND (optional) 6 10 11 12 7 8 9 18 17 16 15 14 13 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 C8051F338/9 Top View P2.3 P2.2 P2.1 P2.0 P1.7 Figure 3.2. QFN-24 Pinout Diagram (Top View) Rev. 0.2 P1.6 31 C8051F336/7/8/9 4. QFN-20 Package Specifications Figure 4.1. QFN-20 Package Drawing Table 4.1. QFN-20 Package Dimensions Dimension A A1 b D D2 e E Min 0.80 0.00 0.18 2.05 Typ 0.90 0.02 0.25 4.00 BSC. 2.15 0.50 BSC. 4.00 BSC. Max 1.00 0.05 0.30 2.25 Dimension E2 L L1 aaa bbb ddd eee Min 2.05 0.30 0.00 -- -- -- -- Typ 2.15 0.40 -- -- -- -- -- Max 2.25 0.50 0.15 0.15 0.10 0.05 0.08 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MO-220, variation VGGD except for custom features D2, E2, and L which are toleranced per supplier designation. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. 32 Rev. 0.2 C8051F336/7/8/9 5. QFN-24 Package Specifications Figure 5.1. QFN-24 Package Drawing Table 5.1. QFN-24 Package Dimensions Dimension A A1 b D D2 e E Min 0.70 0.00 0.18 2.60 Typ 0.75 0.02 0.25 4.00 BSC. 2.70 0.50 BSC. 4.00 BSC. Max 0.80 0.05 0.30 2.80 Dimension E2 L L1 aaa bbb ccc ddd Min 2.60 0.35 0.00 -- -- -- -- Typ 2.70 0.40 -- -- -- -- -- Max 2.80 0.45 0.15 0.15 0.10 0.05 0.08 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC Solid State Outline MO-220, variation WGGD except for custom features D2, E2, and L which are toleranced per supplier designation. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. Rev. 0.2 33 C8051F336/7/8/9 6. 6.1. Electrical Characteristics Absolute Maximum Specifications Table 6.1. Absolute Maximum Ratings Parameter Ambient temperature under bias Storage Temperature Voltage on any Port I/O Pin or RST with respect to GND Voltage on VDD with respect to GND Maximum Total current through VDD or GND Maximum output current sunk by RST or any Port pin Conditions Min -55 -65 -0.3 -0.3 -- -- Typ -- -- -- -- -- -- Max 125 150 5.8 4.2 500 100 Units C C V V mA mA Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 34 Rev. 0.2 C8051F336/7/8/9 6.2. Electrical Characteristics Table 6.2. Global Electrical Characteristics -40 to +85 C, 25 MHz system clock unless otherwise specified. Parameter Digital Supply Voltage Conditions Normal Operation Writing or Erasing Flash Memory Min VRST1 2.7 -- 0 Typ 3.0 3.0 1.5 -- Max 3.6 3.6 -- 25 Units V V V MHz Digital Supply RAM Data Retention Voltage SYSCLK (System Clock) (Note 2) TSYSH (SYSCLK High Time) TSYSL (SYSCLK Low Time) Specified Operating Temperature Range 18 18 -40 -- -- -- -- -- +85 ns ns C Digital Supply Current--CPU Active (Normal Mode, fetching instructions from Flash) IDD (Note 3) VDD = 3.6 V, F = 25 MHz VDD = 3.0 V, F = 25 MHz VDD = 3.0 V, F = 1 MHz VDD = 3.0 V, F = 80 kHz IDD Supply Sensitivity (Note 3) F = 25 MHz F = 1 MHz IDD Frequency Sensitivity (Note 3, Note 4) VDD = 3.0 V, F < 15 MHz, T = 25 C VDD = 3.0 V, F > 15 MHz, T = 25 C VDD = 3.6 V, F < 15 MHz, T = 25 C VDD = 3.6 V, F > 15 MHz, T = 25 C -- -- -- -- -- -- -- -- -- -- 12.3 8.9 0.46 40 TBD TBD TBD TBD TBD TBD TBD TBD -- -- -- -- -- -- -- -- mA mA mA A %/V %/V mA/MHz mA/MHz mA/MHz mA/MHz Digital Supply Current--CPU Inactive (Idle Mode, not fetching instructions from Flash) IDD (Note 3) VDD = 3.6 V, F = 25 MHz VDD = 3.0 V, F = 25 MHz VDD = 3.0 V, F = 1 MHz VDD = 3.0 V, F = 80 kHz -- -- -- -- 6.0 4.4 0.2 16 TBD TBD -- -- mA mA mA A Rev. 0.2 35 C8051F336/7/8/9 Table 6.2. Global Electrical Characteristics (Continued) -40 to +85 C, 25 MHz system clock unless otherwise specified. Parameter IDD Supply Sensitivity (Note 3) F = 25 MHz F = 1 MHz IDD Frequency Sensitivity (Note 3, Note 5) Conditions Min -- -- -- -- -- -- -- Typ TBD TBD TBD TBD TBD TBD < 0.1 Max -- -- -- -- -- -- -- Units %/V %/V mA/MHz mA/MHz mA/MHz mA/MHz A VDD = 3.0 V, F < 1 MHz, T = 25 C VDD = 3.0 V, F > 1 MHz, T = 25 C VDD = 3.6 V, F < 1 MHz, T = 25 C VDD = 3.6 V, F > 1 MHz, T = 25 C Digital Supply Current (Stop or Suspend Mode, shutdown) Oscillator not running, VDD Monitor Disabled Notes: 1. Given in Table 6.4 on page 37. 2. SYSCLK must be at least 32 kHz to enable debugging. 3. Based on device characterization data; Not production tested. 4. IDD can be estimated for frequencies <= 15 MHz by simply multiplying the frequency of interest by the frequency sensitivity number for that range. When using these numbers to estimate IDD for >15 MHz, the estimate should be the current at 25 MHz minus the difference in current indicated by the frequency sensitivity number. For example: VDD = 3.0 V; F = 20 MHz, IDD = 7.8 mA - (25 MHz 20 MHz) * 0.21 mA/MHz = 6.75 mA. 5. Idle IDD can be estimated for frequencies <= 1 MHz by simply multiplying the frequency of interest by the frequency sensitivity number for that range. When using these numbers to estimate Idle IDD for >1 MHz, the estimate should be the current at 25 MHz minus the difference in current indicated by the frequency sensitivity number. For example: VDD = 3.0 V; F = 5 MHz, Idle IDD = 4.8 mA - (25 MHz 5 MHz) * 0.15 mA/MHz = 1.8 mA. Table 6.3. Port I/O DC Electrical Characteristics VDD = 2.7 to 3.6 V, -40 to +85 C unless otherwise specified. Parameters Conditions IOH = -3 mA, Port I/O push-pull IOH = -10 mA, Port I/O push-pull IOL = 8.5 mA Min VDD - 0.7 VDD - 0.1 -- -- -- -- 2.0 -- -- -- Typ -- -- VDD - 0.8 -- -- 1.0 -- -- -- 50 Max -- -- -- 0.6 0.1 -- -- 0.8 1 100 Units V Output High Voltage IOH = -10 A, Port I/O push-pull Output Low Voltage Input High Voltage Input Low Voltage Input Leakage Current IOL = 10 A IOL = 25 mA V V V A Weak Pullup Off Weak Pullup On, VIN = 0 V 36 Rev. 0.2 C8051F336/7/8/9 Table 6.4. Reset Electrical Characteristics -40 to +85 C unless otherwise specified. Parameter RST Output Low Voltage RST Input Low Voltage RST Input Pullup Current VDD POR Threshold (VRST) Missing Clock Detector Timeout Reset Time Delay Minimum RST Low Time to Generate a System Reset VDD Monitor Turn-on Time VDD Monitor Supply Current Conditions IOL = 8.5 mA, VDD = 2.7 V to 3.6 V RST = 0.0 V Min -- -- -- 2.40 Typ -- -- 50 2.55 220 Max 0.6 0.6 100 2.70 600 Units V A V s Time from last system clock rising edge to reset initiation Delay between release of any reset source and code execution at location 0x0000 100 -- -- 40 s 15 100 -- -- -- 20 -- -- 40 s s A Table 6.5. Flash Electrical Characteristics VDD = 2.7 to 3.6 V; -40 to +85 C unless otherwise specified. Parameter Conditions Flash Size Endurance Erase Cycle Time 25 MHz System Clock Write Cycle Time 25 MHz System Clock *Note: 512 bytes at addresses 0x3E00 to 0x3FFF are reserved. Min 16384 20 k 10 40 * Typ -- 100 k 15 55 Max -- -- 20 70 Units bytes Erase/Write ms s Rev. 0.2 37 C8051F336/7/8/9 Table 6.6. Internal High-Frequency Oscillator Electrical Characteristics VDD = 2.7 to 3.6 V; TA = -40 to +85 C unless otherwise specified; Using factory-calibrated settings. Parameter Oscillator Frequency Oscillator Supply Current (from VDD) Power Supply Sensitivity Temperature Sensitivity Conditions IFCN = 11b 25 C, VDD = 3.0 V, OSCICN.7 = 1, OCSICN.5 = 0 Constant Temperature Constant Supply Min 24 -- Typ 24.5 450 Max 25 600 Units MHz A -- -- 0.12 60 -- -- %/V ppm/C Table 6.7. Internal Low-Frequency Oscillator Electrical Characteristics VDD = 2.7 to 3.6 V; TA = -40 to +85 C unless otherwise specified; Using factory-calibrated settings. Parameter Oscillator Frequency Oscillator Supply Current (from VDD) Power Supply Sensitivity Temperature Sensitivity Conditions OSCLD = 11b 25 C, VDD = 3.0 V, OSCLCN.7 = 1 Constant Temperature Constant Supply Min 72 -- -- -- Typ 80 5.5 2.4 30 Max 88 10 -- -- Units kHz A %/V ppm/C 38 Rev. 0.2 C8051F336/7/8/9 Table 6.8. ADC0 Electrical Characteristics VDD = 3.0 V, VREF = 2.40 V (REFSL=0), -40 to +85 C unless otherwise specified. Parameter Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Full Scale Error Offset Temperature Coefficient Signal-to-Noise Plus Distortion Total Harmonic Distortion Spurious-Free Dynamic Range Conversion Rate SAR Conversion Clock Conversion Time in SAR Clocks Track/Hold Acquisition Time Throughput Rate Analog Inputs ADC Input Voltage Range Single Ended (AIN+ - GND) Differential (AIN+ - AIN-) 0 -VREF 0 -- -- Power Specifications Power Supply Current (VDD supplied to ADC0) Power Supply Rejection *Note: Represents one standard deviation from the mean. Conditions DC Accuracy Min Typ 10 Max Units bits -- Guaranteed Monotonic -- -12 -5 -- 53 Up to the 5th harmonic -- -- -- 13 300 -- 0.5 0.5 3 1 3 58 -75 75 -- -- -- -- -- -- 5 5 500 3 1 1 12 5 -- -- -- -- 3.125 -- -- 200 VREF VREF VDD -- -- 900 -- LSB LSB LSB LSB ppm/C dB dB dB MHz clocks ns ksps V V V pF k A mV/V Dynamic performance (10 kHz sine-wave single-ended input, 1 dB below Full Scale, 200 ksps) Absolute Pin Voltage with respect Single Ended or Differential to GND Sampling Capacitance Input Multiplexer Impedance Operating Mode, 200 ksps -- -- Rev. 0.2 39 C8051F336/7/8/9 Table 6.9. Temperature Sensor Electrical Characteristics VDD = 3.0 V, -40 to +85 C unless otherwise specified. Parameter Linearity Relative Accuracy Slope Slope Error* Offset Offset Error* Power Supply Current *Note: Represents one standard deviation from the mean. Conditions Min -- -- -- -- Typ 0.2 TBD TBD TBD TBD TBD TBD Max -- -- -- -- -- -- -- Units C C mV/C V/C mV mV A Temp = 0 C Temp = 0 C -- -- -- Table 6.10. Voltage Reference Electrical Characteristics VDD = 3.0 V; -40 to +85 C unless otherwise specified. Parameter Output Voltage VREF Short-Circuit Current VREF Temperature Coefficient Load Regulation VREF Turn-on Time 1 VREF Turn-on Time 2 Power Supply Rejection External Reference (REFBE = 0) Input Voltage Range Input Current Sample Rate = 200 ksps; VREF = 3.0 V Power Specifications Reference Bias Generator REFBE = `1' or TEMPE = `1' or IDA0EN = `1' -- 30 50 A 0 -- -- TBD VDD -- V A Load = 0 to 200 A to AGND 4.7 F tantalum, 0.1 F ceramic bypass 0.1 F ceramic bypass Conditions Internal Reference (REFBE = 1) 25 C ambient 2.35 -- -- -- -- -- -- 2.42 -- 30 3 7.5 200 -0.6 2.50 10 -- -- -- -- -- V mA ppm/C V/A ms s mV/V Min Typ Max Units 40 Rev. 0.2 C8051F336/7/8/9 Table 6.11. IDAC Electrical Characteristics -40 to +85 C, VDD = 3.0 V Full-scale output current set to 2 mA unless otherwise specified. Parameter Resolution Integral Nonlinearity Differential Nonlinearity Output Compliance Range Offset Error Full Scale Error Full Scale Error Tempco VDD Power Supply Rejection Ratio Dynamic Performance Output Settling Time to 1/2 IDA0H:L = 0x3FF to 0x000 LSB Startup Time Gain Variation 1 mA Full Scale Output Current 0.5 mA Full Scale Output Current Power Consumption 2 mA Full Scale Output Current Power Supply Current (VDD 1 mA Full Scale Output Current supplied to IDAC) 0.5 mA Full Scale Output Current -- -- -- 2100 1100 600 -- -- -- A A A -- -- -- -- 5 5 1 1 -- -- -- -- s s % % 2 mA Full Scale Output Current Guaranteed Monotonic -- -- -- -- -- -- -- Conditions Static Performance 10 0.5 0.5 -- 0 0 30 6 2 1 VDD - 1.2 -- 30 -- -- bits LSB LSB V A A ppm/C A/V Min Typ Max Units Rev. 0.2 41 C8051F336/7/8/9 Table 6.12. Comparator Electrical Characteristics VDD = 3.0 V, -40 to +85 C unless otherwise noted. Parameter Response Time: Mode 0, Vcm* = 1.5 V Response Time: Mode 1, Vcm* = 1.5 V Response Time: Mode 2, Vcm* = 1.5 V Response Time: Mode 3, Vcm* = 1.5 V Common-Mode Rejection Ratio Positive Hysteresis 1 Positive Hysteresis 2 Positive Hysteresis 3 Positive Hysteresis 4 Negative Hysteresis 1 Negative Hysteresis 2 Negative Hysteresis 3 Negative Hysteresis 4 Inverting or Non-Inverting Input Voltage Range Input Capacitance Input Bias Current Input Offset Voltage Power Supply Power Supply Rejection Power-up Time Mode 0 Mode 1 Supply Current at DC Mode 2 Mode 3 Conditions CP0+ - CP0- = 100 mV CP0+ - CP0- = -100 mV CP0+ - CP0- = 100 mV CP0+ - CP0- = -100 mV CP0+ - CP0- = 100 mV CP0+ - CP0- = -100 mV CP0+ - CP0- = 100 mV CP0+ - CP0- = -100 mV Min -- -- -- -- -- -- -- -- -- Typ 100 200 250 350 400 800 1100 5000 1.25 0 5 10 20 0 Max -- -- -- -- -- -- -- -- 5 1 10 20 30 1 10 20 30 VDD + 0.25 -- -- +5 Units ns ns ns ns ns ns ns ns mV/V mV mV mV mV mV mV mV mV V pF nA mV CP0HYP1-0 = 00 CP0HYP1-0 = 01 CP0HYP1-0 = 10 CP0HYP1-0 = 11 CP0HYN1-0 = 00 CP0HYN1-0 = 01 CP0HYN1-0 = 10 CP0HYN1-0 = 11 -- 1 6 12 1 6 12 -0.25 -- -- -5 5 10 20 -- 4 0.001 -- -- -- -- -- -- -- 0.1 10 10 4 2 0.4 -- -- 20 10 5 2.5 mV/V s A A A A *Note: Vcm is the common-mode voltage on CP0+ and CP0-. 42 Rev. 0.2 C8051F336/7/8/9 7. 10-Bit ADC (ADC0, C8051F336/8 only) The ADC0 on the C8051F336/8 is a 200 ksps, 10-bit successive-approximation-register (SAR) ADC with integrated track-and-hold and programmable window detector. The ADC is fully configurable under software control via Special Function Registers. The ADC0 operates in both Single-ended and Differential modes, and may be configured to measure various different signals using the analog multiplexer described in Section "7.4. ADC0 Analog Multiplexer (C8051F336/8 only)" on page 55. The voltage reference for the ADC is selected as described in Section "8. Temperature Sensor (C8051F336/8 only)" on page 58. The ADC0 subsystem is enabled only when the AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic 1. The ADC0 subsystem is in low power shutdown when this bit is logic 0. ADC0CN AD0TM AD0INT AD0BUSY AD0WINT AD0CM2 AD0CM1 AD0CM0 000 001 010 011 100 101 AD0EN VDD Start Conversion AD0BUSY (W) Timer 0 Overflow Timer 2 Overflow Timer 1 Overflow CNVSTR Input Timer 3 Overflow AIN+ From AMUX0 AIN- 10-Bit SAR SYSCLK REF ADC0H ADC ADC0L AD0WINT Window Compare Logic AD0SC0 AD0LJST AD0SC4 AD0SC3 AD0SC2 AD0SC1 32 ADC0LTH ADC0LTL ADC0GTH ADC0GTL ADC0CF Figure 7.1. ADC0 Functional Block Diagram Rev. 0.2 43 C8051F336/7/8/9 7.1. Output Code Formatting The ADC is in Single-ended mode when the negative input is connected to GND. The ADC will be in Differential mode when the negative input is connected to any other option. The output code format differs between Single-ended and Differential modes. The registers ADC0H and ADC0L contain the high and low bytes of the output conversion code from the ADC at the completion of each conversion. Data can be rightjustified or left-justified, depending on the setting of the AD0LJST. When in Single-ended Mode, conversion codes are represented as 10-bit unsigned integers. Inputs are measured from `0' to VREF x 1023/1024. Example codes are shown below for both right-justified and left-justified data. Unused bits in the ADC0H and ADC0L registers are set to `0'. Input Voltage VREF x 1023/1024 VREF x 512/1024 VREF x 256/1024 0 Right-Justified ADC0H:ADC0L (AD0LJST = 0) 0x03FF 0x0200 0x0100 0x0000 Left-Justified ADC0H:ADC0L (AD0LJST = 1) 0xFFC0 0x8000 0x4000 0x0000 When in Differential Mode, conversion codes are represented as 10-bit signed 2's complement numbers. Inputs are measured from -VREF to VREF x 511/512. Example codes are shown below for both right-justified and left-justified data. For right-justified data, the unused MSBs of ADC0H are a sign-extension of the data word. For left-justified data, the unused LSBs in the ADC0L register are set to `0'. Input Voltage VREF x 511/512 VREF x 256/512 0 -VREF x 256/512 -VREF Right-Justified ADC0H:ADC0L (AD0LJST = 0) 0x01FF 0x0100 0x0000 0xFF00 0xFE00 Left-Justified ADC0H:ADC0L (AD0LJST = 1) 0x7FC0 0x4000 0x0000 0xC000 0x8000 7.2. Modes of Operation ADC0 has a maximum conversion speed of 200 ksps. The ADC0 conversion clock is a divided version of the system clock, determined by the AD0SC bits in the ADC0CF register. 7.2.1. Starting a Conversion A conversion can be initiated in one of six ways, depending on the programmed states of the ADC0 Start of Conversion Mode bits (AD0CM2-0) in register ADC0CN. Conversions may be initiated by one of the following: 1. 2. 3. 4. 5. 6. Writing a `1' to the AD0BUSY bit of register ADC0CN A Timer 0 overflow (i.e., timed continuous conversions) A Timer 2 overflow A Timer 1 overflow A rising edge on the CNVSTR input signal (pin P0.6) A Timer 3 overflow Writing a `1' to AD0BUSY provides software control of ADC0 whereby conversions are performed "ondemand". During conversion, the AD0BUSY bit is set to logic 1 and reset to logic 0 when the conversion is complete. The falling edge of AD0BUSY triggers an interrupt (when enabled) and sets the ADC0 interrupt 44 Rev. 0.2 C8051F336/7/8/9 flag (AD0INT). Note: When polling for ADC conversion completions, the ADC0 interrupt flag (AD0INT) should be used. Converted data is available in the ADC0 data registers, ADC0H:ADC0L, when bit AD0INT is logic 1. Note that when Timer 2 or Timer 3 overflows are used as the conversion source, Low Byte overflows are used if Timer 2/3 is in 8-bit mode; High byte overflows are used if Timer 2/3 is in 16-bit mode. See Section "24. Timers" on page 187 for timer configuration. Important Note About Using CNVSTR: The CNVSTR input pin also functions as Port pin P0.6. When the CNVSTR input is used as the ADC0 conversion source, Port pin P0.6 should be skipped by the Digital Crossbar. To configure the Crossbar to skip P0.6, set to `1' Bit6 in register P0SKIP. See Section "20. Port Input/Output" on page 126 for details on Port I/O configuration. 7.2.2. Tracking Modes Each ADC0 conversion must be preceded by a minimum tracking time in order for the converted result to be accurate. The minimum tracking time is given in Table 6.8. The AD0TM bit in register ADC0CN controls the ADC0 track-and-hold mode. In its default state, the ADC0 input is continuously tracked, except when a conversion is in progress. When the AD0TM bit is logic 1, ADC0 operates in low-power track-and-hold mode. In this mode, each conversion is preceded by a tracking period of 3 SAR clocks (after the start-ofconversion signal). When the CNVSTR signal is used to initiate conversions in low-power tracking mode, ADC0 tracks only when CNVSTR is low; conversion begins on the rising edge of CNVSTR (see Figure 7.2). Tracking can also be disabled (shutdown) when the device is in low power standby or sleep modes. Low-power track-and-hold mode is also useful when AMUX settings are frequently changed, due to the settling time requirements described in Section "7.2.3. Settling Time Requirements" on page 47. Rev. 0.2 45 C8051F336/7/8/9 A. ADC0 Timing for External Trigger Source CNVSTR (AD0CM[2:0]=100) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SAR Clocks Low Power or Convert Low Power Mode AD0TM=1 Track Convert AD0TM=0 Track or Convert Convert Track Write '1' to AD0BUSY, Timer 0, Timer 2, Timer 1, Timer 3 Overflow (AD0CM[2:0]=000, 001,010 011, 101) SAR Clocks AD0TM=1 B. ADC0 Timing for Internal Trigger Source 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Low Power Track or Convert Convert Low Power Mode 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SAR Clocks AD0TM=0 Track or Convert Convert Track Figure 7.2. 10-Bit ADC Track and Conversion Example Timing 46 Rev. 0.2 C8051F336/7/8/9 7.2.3. Settling Time Requirements A minimum tracking time is required before each conversion to ensure that an accurate conversion is performed. This tracking time is determined by any series impedance, including the AMUX0 resistance, the the ADC0 sampling capacitance, and the accuracy required for the conversion. Note that in low-power tracking mode, three SAR clocks are used for tracking at the start of every conversion. For many applications, these three SAR clocks will meet the minimum tracking time requirements. Figure 7.3 shows the equivalent ADC0 input circuits for both Differential and Single-ended modes. Notice that the equivalent time constant for both input circuits is the same. The required ADC0 settling time for a given settling accuracy (SA) may be approximated by Equation 7.1. When measuring the Temperature Sensor output or VDD with respect to GND, RTOTAL reduces to RMUX. See Table 6.8 for ADC0 minimum settling time requirements as well as the mux impedance and sampling capacitor values. 2t = ln ------ x R TOTAL C SAMPLE SA Equation 7.1. ADC0 Settling Time Requirements Where: SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB) t is the required settling time in seconds RTOTAL is the sum of the AMUX0 resistance and any external source resistance. n is the ADC resolution in bits (10). n Differential Mode MUX Select Single-Ended Mode MUX Select Px.x RMUX CSAMPLE RCInput= RMUX * CSAMPLE CSAMPLE Px.x RMUX MUX Select Px.x RMUX CSAMPLE RCInput= RMUX * CSAMPLE Figure 7.3. ADC0 Equivalent Input Circuits Rev. 0.2 47 C8051F336/7/8/9 SFR Definition 7.1. ADC0CF: ADC0 Configuration Bit Name Type Reset 1 1 7 6 5 AD0SC[4:0] R/W 1 1 1 4 3 2 AD0LJST R/W 0 R 0 R 0 1 0 SFR Address = 0xBC Bit Name 7:3 Function AD0SC[4:0] ADC0 SAR Conversion Clock Period Bits. SAR Conversion clock is derived from system clock by the following equation, where AD0SC refers to the 5-bit value held in bits AD0SC4-0. SAR Conversion clock requirements are given in the ADC specification table. SYSCLK AD0SC = ---------------------- - 1 CLK SAR 2 AD0LJST ADC0 Left Justify Select. 0: Data in ADC0H:ADC0L registers are right-justified. 1: Data in ADC0H:ADC0L registers are left-justified. 1:0 UNUSED Unused. Read = 00b; Write = don't care. 48 Rev. 0.2 C8051F336/7/8/9 SFR Definition 7.2. ADC0H: ADC0 Data Word MSB Bit Name Type Reset 0 0 0 0 7 6 5 4 3 2 1 0 ADC0H[7:0] R/W 0 0 0 0 SFR Address = 0xBE Bit Name Function 7:0 ADC0H[7:0] ADC0 Data Word High-Order Bits. For AD0LJST = 0: Bits 7-2 are the sign extension of Bit1. Bits 1-0 are the upper 2 bits of the 10-bit ADC0 Data Word. For AD0LJST = 1: Bits 7-0 are the most-significant bits of the 10-bit ADC0 Data Word. SFR Definition 7.3. ADC0L: ADC0 Data Word LSB Bit Name Type Reset 0 0 0 0 7 6 5 4 3 2 1 0 ADC0L[7:0] R/W 0 0 0 0 SFR Address = 0xBD Bit Name 7:0 Function ADC0L[7:0] ADC0 Data Word Low-Order Bits. For AD0LJST = 0: Bits 7-0 are the lower 8 bits of the 10-bit Data Word. For AD0LJST = 1: Bits 7-6 are the lower 2 bits of the 10-bit Data Word. Bits 5-0 will always read `0'. Rev. 0.2 49 C8051F336/7/8/9 SFR Definition 7.4. ADC0CN: ADC0 Control Bit Name Type Reset 7 AD0EN R/W 0 6 AD0TM R/W 0 5 AD0INT R/W 0 4 3 2 1 AD0CM[2:0] R/W 0 0 0 0 AD0BUSY AD0WINT R/W 0 R/W 0 SFR Address = 0xE8; Bit-Addressable Bit Name 7 AD0EN ADC0 Enable Bit. Function 0: ADC0 Disabled. ADC0 is in low-power shutdown. 1: ADC0 Enabled. ADC0 is active and ready for data conversions. 6 AD0TM ADC0 Track Mode Bit. 0: Normal Track Mode: When ADC0 is enabled, tracking is continuous unless a conversion is in progress. Conversion begins immediately on start-of-conversion event, as defined by AD0CM[2:0]. 1: Low-power Track Mode: For AD0CM[2:0] = 100, ADC is tracking when CNVSTR is low, and conversion begins immediately on rising edge of CNVSTR. For all other values of AD0CM[2:0], tracking is initiated on start-of-conversion event, and lasts 3 SAR Clock cycles. The conversion immediately follows this tracking phase. 5 AD0INT ADC0 Conversion Complete Interrupt Flag. 0: ADC0 has not completed a data conversion since AD0INT was last cleared. 1: ADC0 has completed a data conversion. 4 AD0BUSY ADC0 Busy Bit. Read: 0: ADC0 conversion is not in progress. 1: ADC0 conversion is in progress. 3 AD0WINT ADC0 Window Compare Interrupt Flag. 0: ADC0 Window Comparison Data match has not occurred since this flag was last cleared. 1: ADC0 Window Comparison Data match has occurred. 2:0 AD0CM[2:0] ADC0 Start of Conversion Mode Select. 000: ADC0 start-of-conversion source is write of `1' to AD0BUSY. 001: ADC0 start-of-conversion source is overflow of Timer 0. 010: ADC0 start-of-conversion source is overflow of Timer 2. 011: ADC0 start-of-conversion source is overflow of Timer 1. 100: ADC0 start-of-conversion source is rising edge of external CNVSTR. 101: ADC0 start-of-conversion source is overflow of Timer 3. 11x: Reserved. Write: 0: No Effect. 1: Initiates ADC0 Conversion if AD0CM[2:0] = 000b 50 Rev. 0.2 C8051F336/7/8/9 7.3. Programmable Window Detector The ADC Programmable Window Detector continuously compares the ADC0 output registers to user-programmed limits, and notifies the system when a desired condition is detected. This is especially effective in an interrupt-driven system, saving code space and CPU bandwidth while delivering faster system response times. The window detector interrupt flag (AD0WINT in register ADC0CN) can also be used in polled mode. The ADC0 Greater-Than (ADC0GTH, ADC0GTL) and Less-Than (ADC0LTH, ADC0LTL) registers hold the comparison values. The window detector flag can be programmed to indicate when measured data is inside or outside of the user-programmed limits, depending on the contents of the ADC0 Less-Than and ADC0 Greater-Than registers. SFR Definition 7.5. ADC0GTH: ADC0 Greater-Than Data High Byte Bit Name Type Reset 1 1 1 1 7 6 5 4 3 2 1 0 ADC0GTH[7:0] R/W 1 1 1 1 SFR Address = 0xC4 Bit Name 7:0 Function ADC0GTH[7:0] ADC0 Greater-Than Data Word High-Order Bits. SFR Definition 7.6. ADC0GTL: ADC0 Greater-Than Data Low Byte Bit Name Type Reset 1 1 1 1 7 6 5 4 3 2 1 0 ADC0GTL[7:0] R/W 1 1 1 1 SFR Address = 0xC3 Bit Name 7:0 Function ADC0GTL[7:0] ADC0 Greater-Than Data Word Low-Order Bits. Rev. 0.2 51 C8051F336/7/8/9 SFR Definition 7.7. ADC0LTH: ADC0 Less-Than Data High Byte Bit Name Type Reset 0 0 0 0 7 6 5 4 3 2 1 0 ADC0LTH[7:0] R/W 0 0 0 0 SFR Address = 0xC6 Bit Name 7:0 Function ADC0LTH[7:0] ADC0 Less-Than Data Word High-Order Bits. SFR Definition 7.8. ADC0LTL: ADC0 Less-Than Data Low Byte Bit Name Type Reset 0 0 0 0 7 6 5 4 3 2 1 0 ADC0LTL[7:0] R/W 0 0 0 0 SFR Address = 0xC5 Bit Name 7:0 Function ADC0LTL[7:0] ADC0 Less-Than Data Word Low-Order Bits. 52 Rev. 0.2 C8051F336/7/8/9 7.3.1. Window Detector In Single-Ended Mode Figure 7.4 shows two example window comparisons for right-justified, single-ended data, with ADC0LTH:ADC0LTL = 0x0080 (128d) and ADC0GTH:ADC0GTL = 0x0040 (64d). In single-ended mode, the input voltage can range from `0' to VREF x (1023/1024) with respect to GND, and is represented by a 10-bit unsigned integer value. In the left example, an AD0WINT interrupt will be generated if the ADC0 conversion word (ADC0H:ADC0L) is within the range defined by ADC0GTH:ADC0GTL and ADC0LTH:ADC0LTL (if 0x0040 < ADC0H:ADC0L < 0x0080). In the right example, and AD0WINT interrupt will be generated if the ADC0 conversion word is outside of the range defined by the ADC0GT and ADC0LT registers (if ADC0H:ADC0L < 0x0040 or ADC0H:ADC0L > 0x0080). Figure 7.5 shows an example using left-justified data with the same comparison values. ADC0H:ADC0L Input Voltage (Px.x - GND) VREF x (1023/1024) 0x03FF AD0WINT not affected 0x0081 VREF x (128/1024) 0x0080 0x007F AD0WINT=1 VREF x (64/1024) 0x0041 0x0040 0x003F ADC0GTH:ADC0GTL VREF x (64/1024) ADC0LTH:ADC0LTL VREF x (128/1024) Input Voltage (Px.x - GND) VREF x (1023/1024) ADC0H:ADC0L 0x03FF AD0WINT=1 0x0081 0x0080 0x007F 0x0041 0x0040 0x003F ADC0GTH:ADC0GTL AD0WINT not affected ADC0LTH:ADC0LTL AD0WINT not affected 0 0x0000 0 0x0000 AD0WINT=1 Figure 7.4. ADC Window Compare Example: Right-Justified Single-Ended Data ADC0H:ADC0L Input Voltage (Px.x - GND) VREF x (1023/1024) 0xFFC0 AD0WINT not affected 0x2040 VREF x (128/1024) 0x2000 0x1FC0 AD0WINT=1 0x1040 VREF x (64/1024) 0x1000 0x0FC0 ADC0GTH:ADC0GTL VREF x (64/1024) ADC0LTH:ADC0LTL VREF x (128/1024) Input Voltage (Px.x - GND) VREF x (1023/1024) ADC0H:ADC0L 0xFFC0 AD0WINT=1 0x2040 0x2000 0x1FC0 0x1040 0x1000 0x0FC0 ADC0GTH:ADC0GTL AD0WINT not affected ADC0LTH:ADC0LTL AD0WINT not affected 0 0x0000 0 0x0000 AD0WINT=1 Figure 7.5. ADC Window Compare Example: Left-Justified Single-Ended Data Rev. 0.2 53 C8051F336/7/8/9 7.3.2. Window Detector In Differential Mode Figure 7.6 shows two example window comparisons for right-justified, differential data, with ADC0LTH:ADC0LTL = 0x0040 (+64d) and ADC0GTH:ADC0GTH = 0xFFFF (-1d). In differential mode, the measurable voltage between the input pins is between -VREF and VREF x (511/512). Output codes are represented as 10-bit 2s complement signed integers. In the left example, an AD0WINT interrupt will be generated if the ADC0 conversion word (ADC0H:ADC0L) is within the range defined by ADC0GTH:ADC0GTL and ADC0LTH:ADC0LTL (if 0xFFFF (-1d) < ADC0H:ADC0L < 0x0040 (64d)). In the right example, an AD0WINT interrupt will be generated if the ADC0 conversion word is outside of the range defined by the ADC0GT and ADC0LT registers (if ADC0H:ADC0L < 0xFFFF (-1d) or ADC0H:ADC0L > 0x0040 (+64d)). Figure 7.7 shows an example using left-justified data with the same comparison values. ADC0H:ADC0L Input Voltage (Px.x - Px.x) VREF x (511/512) 0x01FF AD0WINT not affected 0x0041 VREF x (64/512) 0x0040 0x003F AD0WINT=1 0x0000 VREF x (-1/512) 0xFFFF 0xFFFE ADC0GTH:ADC0GTL VREF x (-1/512) ADC0LTH:ADC0LTL VREF x (64/512) Input Voltage (Px.x - Px.x) VREF x (511/512) ADC0H:ADC0L 0x01FF AD0WINT=1 0x0041 0x0040 0x003F 0x0000 0xFFFF 0xFFFE ADC0GTH:ADC0GTL AD0WINT not affected ADC0LTH:ADC0LTL AD0WINT not affected -VREF 0x0200 -VREF 0x0200 AD0WINT=1 Figure 7.6. ADC Window Compare Example: Right-Justified Differential Data ADC0H:ADC0L Input Voltage (Px.x - Px.x) VREF x (511/512) 0x7FC0 AD0WINT not affected 0x1040 VREF x (64/512) 0x1000 0x0FC0 AD0WINT=1 0x0000 VREF x (-1/512) 0xFFC0 0xFF80 ADC0GTH:ADC0GTL VREF x (-1/512) ADC0LTH:ADC0LTL VREF x (64/512) Input Voltage (Px.x - Px.y) VREF x (511/512) ADC0H:ADC0L 0x7FC0 AD0WINT=1 0x1040 0x1000 0x0FC0 0x0000 0xFFC0 0xFF80 ADC0GTH:ADC0GTL AD0WINT not affected ADC0LTH:ADC0LTL AD0WINT not affected -VREF 0x8000 -VREF 0x8000 AD0WINT=1 Figure 7.7. ADC Window Compare Example: Left-Justified Differential Data 54 Rev. 0.2 C8051F336/7/8/9 7.4. ADC0 Analog Multiplexer (C8051F336/8 only) ADC0 on the C8051F336/8 has two analog multiplexers, referred to collectively as AMUX0. AMUX0 selects the positive and negative inputs to the ADC. Any of the following may be selected as the positive input: Port I/O pins, the on-chip temperature sensor, or the positive power supply (VDD). Any of the following may be selected as the negative input: Port I/O pins, VREF, or GND. When GND is selected as the negative input, ADC0 operates in Single-ended Mode; all other times, ADC0 operates in Differential Mode. The ADC0 input channels are selected in the AMX0P and AMX0N registers as described in SFR Definition 7.9 and SFR Definition 7.10. P0.0 AMX0P AMX0P4 AMX0P3 AMX0P2 AMX0N2 AMX0P1 AMX0N1 AMX0P0 AMX0N0 AMUX P2.3* Temp Sensor VDD P0.0 AIN+ ADC0 AIN- AMUX AMX0N AMX0N4 *P2.0-P2.3 Only available as inputs on QFN24 Packaging P2.3* VREF GND Figure 7.8. ADC0 Multiplexer Block Diagram Important Note About ADC0 Input Configuration: Port pins selected as ADC0 inputs should be configured as analog inputs, and should be skipped by the Digital Crossbar. To configure a Port pin for analog input, set to `0' the corresponding bit in register PnMDIN. To force the Crossbar to skip a Port pin, set to `1' the corresponding bit in register PnSKIP. See Section "20. Port Input/Output" on page 126 for more Port I/O configuration details. Rev. 0.2 AMX0N3 55 C8051F336/7/8/9 SFR Definition 7.9. AMX0P: AMUX0 Positive Channel Select Bit Name Type Reset R 0 R 0 R 0 1 1 7 6 5 4 3 2 AMX0P[4:0] R/W 1 1 1 1 0 SFR Address = 0xBB Bit Name 7:5 UNUSED Function Unused. Read = 000b; Write = Don't Care. 4:0 AMX0P[4:0] AMUX0 Positive Input Selection. 00000: 00001: 00010: 00011: 00100: 00101: 00110: 00111: 01000: 01001: 01010: 01011: 01100: 01101: 01110: 01111: 10000: 10001: 10010: 10011: 10100: 10101: 10110 - 11111: P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 Temp Sensor VDD P2.0 (C8051F338/9 Only) P2.1 (C8051F338/9 Only) P2.2 (C8051F338/9 Only) P2.3 (C8051F338/9 Only) no input selected 56 Rev. 0.2 C8051F336/7/8/9 SFR Definition 7.10. AMX0N: AMUX0 Negative Channel Select Bit Name Type Reset R 0 R 0 R 0 1 1 7 6 5 4 3 2 AMX0N[4:0] R/W 1 1 1 1 0 SFR Address = 0xBA Bit Name 7:5 UNUSED Function Unused. Read = 000b; Write = Don't Care. 4:0 AMX0N[4:0] AMUX0 Negative Input Selection. 00000: 00001: 00010: 00011: 00100: 00101: 00110: 00111: 01000: 01001: 01010: 01011: 01100: 01101: 01110: 01111: 10000: 10001: 10010: 10011: 10100: 10101: 10110 - 11111: P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 VREF GND (ADC in Single-Ended Mode) P2.0 (C8051F338/9 Only) P2.1 (C8051F338/9 Only) P2.2 (C8051F338/9 Only) P2.3 (C8051F338/9 Only) no input selected Rev. 0.2 57 C8051F336/7/8/9 8. Temperature Sensor (C8051F336/8 only) An on-chip temperature sensor is included on the C8051F336/8 which can be directly accessed via the ADC multiplexer in single-ended configuration. To use the ADC to measure the temperature sensor, the positive ADC mux channel should be configured to connect to the temperature sensor and the negative ADC mux channel should be configured to connect to GND. The temperature sensor transfer function is shown in Figure 8.1. The output voltage (VTEMP) is the positive ADC input when the ADC multiplexer is set correctly. The TEMPE bit in register REF0CN enables/disables the temperature sensor, as described in SFR Definition 10.1. While disabled, the temperature sensor defaults to a high impedance state and any ADC measurements performed on the sensor will result in meaningless data. Refer to Table 6.9 for the slope and offset parameters of the temperature sensor. VTEMP = (Slope x TempC) + Offset TempC = (VTEMP - Offset) / Slope Slope (V / deg C) Offset (V at 0 Celsius) Voltage Temperature Figure 8.1. Temperature Sensor Transfer Function 58 Rev. 0.2 C8051F336/7/8/9 9. 10-Bit Current Mode DAC (IDA0, C8051F336/8 only) The C8051F336/8 device includes a 10-bit current-mode Digital-to-Analog Converter (IDAC). The maximum current output of the IDAC can be adjusted for three different current settings; 0.5 mA, 1 mA, and 2 mA. The IDAC is enabled or disabled with the IDA0EN bit in the IDA0 Control Register (see SFR Definition 9.1). When IDA0EN is set to `0', the IDAC port pin (P0.1) behaves as a normal GPIO pin. When IDA0EN is set to `1', the digital output drivers and weak pullup for the IDAC pin are automatically disabled, and the pin is connected to the IDAC output. An internal bandgap bias generator is used to generate a reference current for the IDAC whenever it is enabled. When using the IDAC, bit 1 in the P0SKIP register should be set to `1', to force the Crossbar to skip the IDAC pin. 9.1. IDA0 Output Scheduling IDA0 features a flexible output update mechanism which allows for seamless full-scale changes and supports jitter-free updates for waveform generation. Three update modes are provided, allowing IDAC output updates on a write to IDA0H, on a Timer overflow, or on an external pin edge. 9.1.1. Update Output On-Demand In its default mode (IDA0CN.[6:4] = `111') the IDA0 output is updated "on-demand" on a write to the highbyte of the IDA0 data register (IDA0H). It is important to note that writes to IDA0L are held in this mode, and have no effect on the IDA0 output until a write to IDA0H takes place. If writing a full 10-bit word to the IDAC data registers, the 10-bit data word is written to the low byte (IDA0L) and high byte (IDA0H) data registers. Data is latched into IDA0 after a write to the IDA0H register, so the write sequence should be IDA0L followed by IDA0H if the full 10-bit resolution is required. The IDAC can be used in 8-bit mode by initializing IDA0L to the desired value (typically 0x00), and writing data to only IDA0H (see Section 9.2 for information on the format of the 10-bit IDAC data word within the 16-bit SFR space). IDA0H IDA0CN IDA0EN IDA0CM2 IDA0CM1 IDA0CM0 IDA0OMD1 IDA0OMD0 IDA0H 8 10 Latch IDA0 IDA0 IDA0L 2 Figure 9.1. IDA0 Functional Block Diagram CNVSTR Rev. 0.2 Timer 0 Timer 1 Timer 2 Timer 3 59 C8051F336/7/8/9 9.1.2. Update Output Based on Timer Overflow Similar to the ADC operation, in which an ADC conversion can be initiated by a timer overflow independently of the processor, the IDAC outputs can use a Timer overflow to schedule an output update event. This feature is useful in systems where the IDAC is used to generate a waveform of a defined sampling rate by eliminating the effects of variable interrupt latency and instruction execution on the timing of the IDAC output. When the IDA0CM bits (IDA0CN.[6:4]) are set to `000', `001', `010' or `011', writes to both IDAC data registers (IDA0L and IDA0H) are held until an associated Timer overflow event (Timer 0, Timer 1, Timer 2 or Timer 3, respectively) occurs, at which time the IDA0H:IDA0L contents are copied to the IDAC input latches, allowing the IDAC output to change to the new value. 9.1.3. Update Output Based on CNVSTR Edge The IDAC output can also be configured to update on a rising edge, falling edge, or both edges of the external CNVSTR signal. When the IDA0CM bits (IDA0CN.[6:4]) are set to `100', `101', or `110', writes to both IDAC data registers (IDA0L and IDA0H) are held until an edge occurs on the CNVSTR input pin. The particular setting of the IDA0CM bits determines whether IDAC outputs are updated on rising, falling, or both edges of CNVSTR. When a corresponding edge occurs, the IDA0H:IDA0L contents are copied to the IDAC input latches, allowing the IDAC output to change to the new value. 9.2. IDAC Output Mapping The IDAC data registers (IDA0H and IDA0L) are left-justified, meaning that the eight MSBs of the IDAC output word are mapped to bits 7-0 of the IDA0H register, and the two LSBs of the IDAC output word are mapped to bits 7 and 6 of the IDA0L register. The data word mapping for the IDAC is shown in Figure 9.2. IDA0H IDA09 IDA08 IDA07 IDA06 IDA05 IDA04 IDA03 IDA02 IDA01 IDA00 IDA0L Input Data Word (IDA09-IDA00) 0x000 0x001 0x200 0x3FF Output Current IDA0OMD[1:0] = `1x' 0 mA 1/1024 x 2 mA 512/1024 x 2 mA 1023/1024 x 2 mA Output Current IDA0OMD[1:0] = `01' 0 mA 1/1024 x 1 mA 512/1024 x 1 mA 1023/1024 x 1 mA Output Current IDA0OMD[1:0] = `00' 0 mA 1/1024 x 0.5 mA 512/1024 x 0.5 mA 1023/1024 x 0.5 mA Figure 9.2. IDA0 Data Word Mapping The full-scale output current of the IDAC is selected using the IDA0OMD bits (IDA0CN[1:0]). By default, the IDAC is set to a full-scale output current of 2 mA. The IDA0OMD bits can also be configured to provide full-scale output currents of 1 mA or 0.5 mA, as shown in SFR Definition 9.1. 60 Rev. 0.2 C8051F336/7/8/9 SFR Definition 9.1. IDA0CN: IDA0 Control Bit Name Type Reset 7 IDA0EN R/W 0 1 6 5 IDA0CM[2:0] R/W 1 1 R 0 R 0 1 4 3 2 1 0 IDA0OMD[1:0] R/W 0 SFR Address = 0xB9 Bit Name 7 IDA0EN IDA0 Enable. 0: IDA0 Disabled. 1: IDA0 Enabled. 6:4 IDA0CM[2:0] IDA0 Update Source Select bits. Function 000: DAC output updates on Timer 0 overflow. 001: DAC output updates on Timer 1 overflow. 010: DAC output updates on Timer 2 overflow. 011: DAC output updates on Timer 3 overflow. 100: DAC output updates on rising edge of CNVSTR. 101: DAC output updates on falling edge of CNVSTR. 110: DAC output updates on any edge of CNVSTR. 111: DAC output updates on write to IDA0H. 3:2 UNUSED Unused. Read = 00b. Write = Don't care. 00: 0.5 mA full-scale output current. 01: 1.0 mA full-scale output current. 1x: 2.0 mA full-scale output current. 1:0 IDA0OMD[1:0] IDA0 Output Mode Select bits. Rev. 0.2 61 C8051F336/7/8/9 SFR Definition 9.2. IDA0H: IDA0 Data Word MSB Bit Name Type Reset 0 0 0 0 7 6 5 4 IDA0[9:2] R/W 0 0 0 0 3 2 1 0 SFR Address = 0x97 Bit Name 7:0 IDA0[9:2] IDA0 Data Word High-Order Bits. Function Upper 8 bits of the 10-bit IDA0 Data Word. SFR Definition 9.3. IDA0L: IDA0 Data Word LSB Bit Name Type Reset 0 7 IDA0[1:0] R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 6 5 4 3 2 1 0 SFR Address = 0x96 Bit Name 7:6 5:0 IDA0[1:0] UNUSED IDA0 Data Word Low-Order Bits. Function Lower 2 bits of the 10-bit IDA0 Data Word. Unused. Read = 000000b. Write = Don't care. 62 Rev. 0.2 C8051F336/7/8/9 10. Voltage Reference (C8051F336/8 only) The Voltage reference multiplexer for the ADC is configurable to use an externally connected voltage reference, the on-chip reference voltage generator routed to the VREF pin, or the VDD power supply voltage (see Figure 10.1). The REFSL bit in the Reference Control register (REF0CN, SFR Definition 10.1) selects the reference source for the ADC. For an external source or the on-chip reference, REFSL should be set to `0' to select the VREF pin. To use VDD as the reference source, REFSL should be set to `1'. The BIASE bit enables the internal voltage bias generator, which is used by many of the analog peripherals on the device. This bias is automatically enabled when any peripheral which requires it is enabled, and it does not need to be enabled manually. The bias generator may be enabled manually by writing a `1' to the BIASE bit in register REF0CN. The electrical specifications for the voltage reference circuit are given in Table 6.10. The on-chip voltage reference circuit consists of a 1.2 V, temperature stable bandgap voltage reference generator and a gain-of-two output buffer amplifier. The on-chip voltage reference can be driven on the VREF pin by setting the REFBE bit in register REF0CN to a `1'. The maximum load seen by the VREF pin must be less than 200 A to GND. Bypass capacitors of 0.1 F and 4.7 F are recommended from the VREF pin to GND. If the on-chip reference is not used, the REFBE bit should be cleared to `0'. Electrical specifications for the on-chip voltage reference are given in Table 6.10. Important Note about the VREF Pin: When using either an external voltage reference or the on-chip reference circuitry, the VREF pin should be configured as an analog pin and skipped by the Digital Crossbar. Refer to Section "20. Port Input/Output" on page 126 for the location of the VREF pin, as well as details of how to configure the pin in analog mode and to be skipped by the crossbar. REF0CN REFSL TEMPE BIASE REFBE EN IOSCE N EN VREF Bias Generator To ADC, IDAC, Internal Oscillators VDD R1 External Voltage Reference Circuit 0 Temp Sensor To Analog Mux VREF (to ADC) GND VDD 1 REFBE 4.7F + 0.1F EN Recommended Bypass Capacitors Internal Reference Figure 10.1. Voltage Reference Functional Block Diagram Rev. 0.2 63 C8051F336/7/8/9 SFR Definition 10.1. REF0CN: Reference Control Bit Name Type Reset R 0 R 0 R 0 R 0 7 6 5 4 3 REFSL R/W 0 2 TEMPE R/W 0 1 BIASE R/W 0 0 REFBE R/W 0 SFR Address = 0xD1 Bit Name 7:4 3 Function UNUSED Unused. Read = 0000b; Write = don't care. REFSL Voltage Reference Select. This bit selects the ADCs voltage reference. 0: VREF pin used as voltage reference. 1: VDD used as voltage reference. 2 TEMPE Temperature Sensor Enable Bit. 0: Internal Temperature Sensor off. 1: Internal Temperature Sensor on. 1 BIASE Internal Analog Bias Generator Enable Bit. 0: Internal Bias Generator off. 1: Internal Bias Generator on. 0 REFBE On-chip Reference Buffer Enable Bit. 0: On-chip Reference Buffer off. 1: On-chip Reference Buffer on. Internal voltage reference driven on the VREF pin. 64 Rev. 0.2 C8051F336/7/8/9 11. Comparator0 C8051F336/7/8/9 devices include an on-chip programmable voltage comparator, Comparator0, shown in Figure 11.1. The Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two outputs that are optionally available at the Port pins: a synchronous "latched" output (CP0), or an asynchronous "raw" output (CP0A). The asynchronous CP0A signal is available even when the system clock is not active. This allows the Comparator to operate and generate an output with the device in STOP mode. When assigned to a Port pin, the Comparator output may be configured as open drain or push-pull (see Section "20.4. Port I/O Initialization" on page 133). Comparator0 may also be used as a reset source (see Section "18.5. Comparator0 Reset" on page 114). The Comparator0 inputs are selected by the comparator input multiplexer, as detailed in Section "11.1. Comparator Multiplexer" on page 70. CPT0CN CP0HYN0 CP0 + Comparator Input Mux CP0 CP0HYN1 CP0HYP1 CP0HYP0 CP0OUT CP0RIF CP0FIF CP0EN VDD + D SET CP0 Q D SET Q GND CLR Q CLR Q Crossbar (SYNCHRONIZER) CP0A Reset Decision Tree CP0 Interrupt CPT0MD CP0MD0 CP0MD1 CP0RIE CP0FIE CP0RIF CP0FIF 0 1 0 1 CP0EN 0 1 EA 0 1 Figure 11.1. Comparator0 Functional Block Diagram Rev. 0.2 65 C8051F336/7/8/9 The Comparator output can be polled in software, used as an interrupt source, and/or routed to a Port pin. When routed to a Port pin, the Comparator output is available asynchronous or synchronous to the system clock; the asynchronous output is available even in STOP mode (with no system clock active). When disabled, the Comparator output (if assigned to a Port I/O pin via the Crossbar) defaults to the logic low state, and the power supply to the comparator is turned off. See Section "20.3. Priority Crossbar Decoder" on page 131 for details on configuring Comparator outputs via the digital Crossbar. Comparator inputs can be externally driven from -0.25 V to (VDD) + 0.25 V without damage or upset. The complete Comparator electrical specifications are given in Table 6.12. The Comparator response time may be configured in software via the CPT0MD register (see SFR Definition 11.2). Selecting a longer response time reduces the Comparator supply current. VIN+ VIN- CP0+ CP0- + CP0 _ OUT CIRCUIT CONFIGURATION Positive Hysteresis Voltage (Programmed with CP0HYP Bits) VIN- INPUTS VIN+ Negative Hysteresis Voltage (Programmed by CP0HYN Bits) VOH OUTPUT VOL Negative Hysteresis Disabled Positive Hysteresis Disabled Maximum Positive Hysteresis Maximum Negative Hysteresis Figure 11.2. Comparator Hysteresis Plot The Comparator hysteresis is software-programmable via its Comparator Control register CPT0CN. The user can program both the amount of hysteresis voltage (referred to the input voltage) and the positive and negative-going symmetry of this hysteresis around the threshold voltage. The Comparator hysteresis is programmed using Bits3-0 in the Comparator Control Register CPT0CN (shown in SFR Definition 11.1). The amount of negative hysteresis voltage is determined by the settings of the CP0HYN bits. As shown in Figure 11.2, settings of 20, 10 or 5 mV of negative hysteresis can be programmed, or negative hysteresis can be disabled. In a similar way, the amount of positive hysteresis is determined by the setting the CP0HYP bits. Comparator interrupts can be generated on both rising-edge and falling-edge output transitions. (For Interrupt enable and priority control, see Section "15.1. MCU Interrupt Sources and Vectors" on page 90). The CP0FIF flag is set to logic 1 upon a Comparator falling-edge occurrence, and the CP0RIF flag is set to 66 Rev. 0.2 C8051F336/7/8/9 logic 1 upon the Comparator rising-edge occurrence. Once set, these bits remain set until cleared by software. The Comparator rising-edge interrupt mask is enabled by setting CP0RIE to a logic 1. The Comparator0 falling-edge interrupt mask is enabled by setting CP0FIE to a logic 1. The output state of the Comparator can be obtained at any time by reading the CP0OUT bit. The Comparator is enabled by setting the CP0EN bit to logic 1, and is disabled by clearing this bit to logic 0. Note that false rising edges and falling edges can be detected when the comparator is first powered on or if changes are made to the hysteresis or response time control bits. Therefore, it is recommended that the rising-edge and falling-edge flags be explicitly cleared to logic 0 a short time after the comparator is enabled or its mode bits have been changed. Rev. 0.2 67 C8051F336/7/8/9 SFR Definition 11.1. CPT0CN: Comparator0 Control Bit Name Type Reset 7 CP0EN R/W 0 6 CP0OUT R 0 5 CP0RIF R/W 0 4 CP0FIF R/W 0 0 3 2 1 0 CP0HYP[1:0] R/W 0 CP0HYN[1:0] R/W 0 0 SFR Address = 0x9B Bit Name 7 CP0EN Comparator0 Enable Bit. 0: Comparator0 Disabled. 1: Comparator0 Enabled. 6 CP0OUT Comparator0 Output State Flag. 0: Voltage on CP0+ < CP0-. 1: Voltage on CP0+ > CP0-. 5 CP0RIF Function Comparator0 Rising-Edge Flag. Must be cleared by software. 0: No Comparator0 Rising Edge has occurred since this flag was last cleared. 1: Comparator0 Rising Edge has occurred. 4 CP0FIF Comparator0 Falling-Edge Flag. Must be cleared by software. 0: No Comparator0 Falling-Edge has occurred since this flag was last cleared. 1: Comparator0 Falling-Edge has occurred. 3:2 CP0HYP[1:0] Comparator0 Positive Hysteresis Control Bits. 00: Positive Hysteresis Disabled. 01: Positive Hysteresis = 5 mV. 10: Positive Hysteresis = 10 mV. 11: Positive Hysteresis = 20 mV. 1:0 CP0HYN[1:0] Comparator0 Negative Hysteresis Control Bits. 00: Negative Hysteresis Disabled. 01: Negative Hysteresis = 5 mV. 10: Negative Hysteresis = 10 mV. 11: Negative Hysteresis = 20 mV. 68 Rev. 0.2 C8051F336/7/8/9 SFR Definition 11.2. CPT0MD: Comparator0 Mode Selection Bit Name Type Reset R 0 R 0 7 6 5 CP0RIE R/W 0 4 CP0FIE R/W 0 R 0 R 0 1 3 2 1 0 CP0MD[1:0] R/W 0 SFR Address = 0x9D Bit Name 7:6 5 UNUSED CP0RIE Function Unused. Read = 00b, Write = Don't Care. Comparator0 Rising-Edge Interrupt Enable. 0: Comparator0 Rising-edge interrupt disabled. 1: Comparator0 Rising-edge interrupt enabled. Comparator0 Falling-Edge Interrupt Enable. 0: Comparator0 Falling-edge interrupt disabled. 1: Comparator0 Falling-edge interrupt enabled. Unused. Read = 00b, Write = don't care. 4 CP0FIE 3:2 1:0 UNUSED CP0MD[1:0] Comparator0 Mode Select. These bits affect the response time and power consumption for Comparator0. 00: Mode 0 (Fastest Response Time, Highest Power Consumption) 01: Mode 1 10: Mode 2 11: Mode 3 (Slowest Response Time, Lowest Power Consumption) Rev. 0.2 69 C8051F336/7/8/9 11.1. Comparator Multiplexer C8051F336/7/8/9 devices include an analog input multiplexer to connect Port I/O pins to the comparator inputs. The Comparator0 inputs are selected in the CPT0MX register (SFR Definition 11.3). The CMX0P1- CMX0P0 bits select the Comparator0 positive input; the CMX0N1-CMX0N0 bits select the Comparator0 negative input. Important Note About Comparator Inputs: The Port pins selected as comparator inputs should be configured as analog inputs in their associated Port configuration register, and configured to be skipped by the Crossbar (for details on Port configuration, see Section "20.6. Special Function Registers for Accessing and Configuring Port I/O" on page 138). CPT0MX CMX0N3 CMX0N2 CMX0N1 CMX0N0 CMX0P3 CMX0P2 CMX0P1 CMX0P0 P0.0 P0.2 P0.4 P0.6 P1.0 P1.2 P1.4 P1.6 P2.0* P2.2* P0.1 P0.3 P0.5 P0.7 P1.1 P1.3 P1.5 P1.7 P2.1* P2.3* VDD CP0 + + CP0 - GND *P2.0-P2.3 Only available as inputs on QFN24 Packaging Figure 11.3. Comparator Input Multiplexer Block Diagram 70 Rev. 0.2 C8051F336/7/8/9 SFR Definition 11.3. CPT0MX: Comparator0 MUX Selection Bit Name Type Reset 1 1 7 6 5 4 3 2 1 0 CMX0N[3:0] R/W 1 1 1 CMX0P[3:0] R/W 1 1 1 SFR Address = 0x9F Bit Name 7:4 Function CMX0N[3:0] Comparator0 Negative Input MUX Selection. 0000: 0001: 0010: 0011: 0100: 0101: 0110: 0111: 1000: 1001: 1010-1111: P0.1 P0.3 P0.5 P0.7 P1.1 P1.3 P1.5 P1.7 P2.1 (C8051F338/9 Only) P2.3 (C8051F338/9 Only) None P0.0 P0.2 P0.4 P0.6 P1.0 P1.2 P1.4 P1.6 P2.0 (C8051F338/9 Only) P2.2 (C8051F338/9 Only) None 3:0 CMX0P[3:0] Comparator0 Positive Input MUX Selection. 0000: 0001: 0010: 0011: 0100: 0101: 0110: 0111: 1000: 1001: 1010-1111: Rev. 0.2 71 C8051F336/7/8/9 12. CIP-51 Microcontroller The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51TM instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The MCU family has a superset of all the peripherals included with a standard 8051. The CIP-51 also includes on-chip debug hardware (see description in Section 26), and interfaces directly with the analog and digital subsystems providing a complete data acquisition or control-system solution in a single integrated circuit. The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as additional custom peripherals and functions to extend its capability (see Figure 12.1 for a block diagram). The CIP-51 includes the following features: - Fully Compatible with MCS-51 Instruction Set - 25 MIPS Peak Throughput with 25 MHz Clock - 0 to 25 MHz Clock Frequency Extended Interrupt Handler Reset Input Power Management Modes On-chip Debug Logic Program and Data Memory Security Performance The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to execute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51 core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more than eight system clock cycles. DATA BUS D8 D8 D8 D8 D8 ACCUMULATOR B REGISTER STACK POINTER DATA BUS TMP1 TMP2 PSW ALU D8 D8 SRAM ADDRESS REGISTER D8 SRAM DATA BUS SFR_ADDRESS BUFFER D8 DATA POINTER D8 D8 SFR BUS INTERFACE SFR_CONTROL SFR_WRITE_DATA SFR_READ_DATA PC INCREMENTER DATA BUS D8 PROGRAM COUNTER (PC) MEM_ADDRESS MEM_CONTROL PRGM. ADDRESS REG. A16 MEMORY INTERFACE MEM_WRITE_DATA MEM_READ_DATA PIPELINE RESET CLOCK STOP IDLE POWER CONTROL REGISTER D8 D8 CONTROL LOGIC INTERRUPT INTERFACE SYSTEM_IRQs EMULATION_IRQ D8 Figure 12.1. CIP-51 Block Diagram 72 Rev. 0.2 D8 C8051F336/7/8/9 With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that require each execution time. Clocks to Execute Number of Instructions 1 26 2 50 2/3 5 3 14 3/4 7 4 3 4/5 1 5 2 8 1 Programming and Debugging Support In-system programming of the Flash program memory and communication with on-chip debug support logic is accomplished via the Silicon Labs 2-Wire Development Interface (C2). The on-chip debug support logic facilitates full speed in-circuit debugging, allowing the setting of hardware breakpoints, starting, stopping and single stepping through program execution (including interrupt service routines), examination of the program's call stack, and reading/writing the contents of registers and memory. This method of on-chip debugging is completely non-intrusive, requiring no RAM, Stack, timers, or other on-chip resources. C2 details can be found in Section "26. C2 Interface" on page 229. The CIP-51 is supported by development tools from Silicon Labs and third party vendors. Silicon Labs provides an integrated development environment (IDE) including editor, debugger and programmer. The IDE's debugger and programmer interface to the CIP-51 via the C2 interface to provide fast and efficient in-system device programming and debugging. Third party macro assemblers and C compilers are also available. 12.1. Instruction Set The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51TM instruction set. Standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51 instructions are the binary and functional equivalent of their MCS-51TM counterparts, including opcodes, addressing modes and effect on PSW flags. However, instruction timing is different than that of the standard 8051. 12.1.1. Instruction and CPU Timing In many 8051 implementations, a distinction is made between machine cycles and clock cycles, with machine cycles varying from 2 to 12 clock cycles in length. However, the CIP-51 implementation is based solely on clock cycle timing. All instruction timings are specified in terms of clock cycles. Due to the pipelined architecture of the CIP-51, most instructions execute in the same number of clock cycles as there are program bytes in the instruction. Conditional branch instructions take one less clock cycle to complete when the branch is not taken as opposed to when the branch is taken. Table 12.1 is the CIP-51 Instruction Set Summary, which includes the mnemonic, number of bytes, and number of clock cycles for each instruction. Rev. 0.2 73 C8051F336/7/8/9 Table 12.1. CIP-51 Instruction Set Summary Mnemonic Description Arithmetic Operations Add register to A Add direct byte to A Add indirect RAM to A Add immediate to A Add register to A with carry Add direct byte to A with carry Add indirect RAM to A with carry Add immediate to A with carry Subtract register from A with borrow Subtract direct byte from A with borrow Subtract indirect RAM from A with borrow Subtract immediate from A with borrow Increment A Increment register Increment direct byte Increment indirect RAM Decrement A Decrement register Decrement direct byte Decrement indirect RAM Increment Data Pointer Multiply A and B Divide A by B Decimal adjust A Logical Operations AND Register to A AND direct byte to A AND indirect RAM to A AND immediate to A AND A to direct byte AND immediate to direct byte OR Register to A OR direct byte to A OR indirect RAM to A OR immediate to A OR A to direct byte OR immediate to direct byte Exclusive-OR Register to A Exclusive-OR direct byte to A Exclusive-OR indirect RAM to A Exclusive-OR immediate to A Exclusive-OR A to direct byte Exclusive-OR immediate to direct byte Bytes Clock Cycles 1 2 2 2 1 2 2 2 1 2 2 2 1 1 2 2 1 1 2 2 1 4 8 1 1 2 2 2 2 3 1 2 2 2 2 3 1 2 2 2 2 3 ADD A, Rn ADD A, direct ADD A, @Ri ADD A, #data ADDC A, Rn ADDC A, direct ADDC A, @Ri ADDC A, #data SUBB A, Rn SUBB A, direct SUBB A, @Ri SUBB A, #data INC A INC Rn INC direct INC @Ri DEC A DEC Rn DEC direct DEC @Ri INC DPTR MUL AB DIV AB DA A ANL A, Rn ANL A, direct ANL A, @Ri ANL A, #data ANL direct, A ANL direct, #data ORL A, Rn ORL A, direct ORL A, @Ri ORL A, #data ORL direct, A ORL direct, #data XRL A, Rn XRL A, direct XRL A, @Ri XRL A, #data XRL direct, A XRL direct, #data 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 1 1 1 2 1 1 1 1 1 1 2 1 2 2 3 1 2 1 2 2 3 1 2 1 2 2 3 74 Rev. 0.2 C8051F336/7/8/9 Table 12.1. CIP-51 Instruction Set Summary (Continued) Mnemonic CLR A CPL A RL A RLC A RR A RRC A SWAP A MOV A, Rn MOV A, direct MOV A, @Ri MOV A, #data MOV Rn, A MOV Rn, direct MOV Rn, #data MOV direct, A MOV direct, Rn MOV direct, direct MOV direct, @Ri MOV direct, #data MOV @Ri, A MOV @Ri, direct MOV @Ri, #data MOV DPTR, #data16 MOVC A, @A+DPTR MOVC A, @A+PC MOVX A, @Ri MOVX @Ri, A MOVX A, @DPTR MOVX @DPTR, A PUSH direct POP direct XCH A, Rn XCH A, direct XCH A, @Ri XCHD A, @Ri CLR C CLR bit SETB C SETB bit CPL C CPL bit ANL C, bit Description Clear A Complement A Rotate A left Rotate A left through Carry Rotate A right Rotate A right through Carry Swap nibbles of A Data Transfer Move Register to A Move direct byte to A Move indirect RAM to A Move immediate to A Move A to Register Move direct byte to Register Move immediate to Register Move A to direct byte Move Register to direct byte Move direct byte to direct byte Move indirect RAM to direct byte Move immediate to direct byte Move A to indirect RAM Move direct byte to indirect RAM Move immediate to indirect RAM Load DPTR with 16-bit constant Move code byte relative DPTR to A Move code byte relative PC to A Move external data (8-bit address) to A Move A to external data (8-bit address) Move external data (16-bit address) to A Move A to external data (16-bit address) Push direct byte onto stack Pop direct byte from stack Exchange Register with A Exchange direct byte with A Exchange indirect RAM with A Exchange low nibble of indirect RAM with A Boolean Manipulation Clear Carry Clear direct bit Set Carry Set direct bit Complement Carry Complement direct bit AND direct bit to Carry Bytes 1 1 1 1 1 1 1 1 2 1 2 1 2 2 2 2 3 2 3 1 2 2 3 1 1 1 1 1 1 2 2 1 2 1 1 1 2 1 2 1 2 2 Clock Cycles 1 1 1 1 1 1 1 1 2 2 2 1 2 2 2 2 3 2 3 2 2 2 3 3 3 3 3 3 3 2 2 1 2 2 2 1 2 1 2 1 2 2 Rev. 0.2 75 C8051F336/7/8/9 Table 12.1. CIP-51 Instruction Set Summary (Continued) Mnemonic ANL C, /bit ORL C, bit ORL C, /bit MOV C, bit MOV bit, C JC rel JNC rel JB bit, rel JNB bit, rel JBC bit, rel ACALL addr11 LCALL addr16 RET RETI AJMP addr11 LJMP addr16 SJMP rel JMP @A+DPTR JZ rel JNZ rel CJNE A, direct, rel CJNE A, #data, rel CJNE Rn, #data, rel CJNE @Ri, #data, rel DJNZ Rn, rel DJNZ direct, rel NOP Description AND complement of direct bit to Carry OR direct bit to carry OR complement of direct bit to Carry Move direct bit to Carry Move Carry to direct bit Jump if Carry is set Jump if Carry is not set Jump if direct bit is set Jump if direct bit is not set Jump if direct bit is set and clear bit Program Branching Absolute subroutine call Long subroutine call Return from subroutine Return from interrupt Absolute jump Long jump Short jump (relative address) Jump indirect relative to DPTR Jump if A equals zero Jump if A does not equal zero Compare direct byte to A and jump if not equal Compare immediate to A and jump if not equal Compare immediate to Register and jump if not equal Compare immediate to indirect and jump if not equal Decrement Register and jump if not zero Decrement direct byte and jump if not zero No operation Bytes 2 2 2 2 2 2 2 3 3 3 2 3 1 1 2 3 2 1 2 2 3 3 3 3 2 3 1 Clock Cycles 2 2 2 2 2 2/3 2/3 3/4 3/4 3/4 3 4 5 5 3 4 3 3 2/3 2/3 3/4 3/4 3/4 4/5 2/3 3/4 1 76 Rev. 0.2 C8051F336/7/8/9 Notes on Registers, Operands and Addressing Modes: Rn - Register R0-R7 of the currently selected register bank. @Ri - Data RAM location addressed indirectly through R0 or R1. rel - 8-bit, signed (two's complement) offset relative to the first byte of the following instruction. Used by SJMP and all conditional jumps. direct - 8-bit internal data location's address. This could be a direct-access Data RAM location (0x00- 0x7F) or an SFR (0x80-0xFF). #data - 8-bit constant #data16 - 16-bit constant bit - Direct-accessed bit in Data RAM or SFR addr11 - 11-bit destination address used by ACALL and AJMP. The destination must be within the same 2 kB page of program memory as the first byte of the following instruction. addr16 - 16-bit destination address used by LCALL and LJMP. The destination may be anywhere within the 8 kB program memory space. There is one unused opcode (0xA5) that performs the same function as NOP. All mnemonics copyrighted (c) Intel Corporation 1980. Rev. 0.2 77 C8051F336/7/8/9 12.2. CIP-51 Register Descriptions Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits should not be set to logic 1. Future product versions may use these bits to implement new features in which case the reset value of the bit will be logic 0, selecting the feature's default state. Detailed descriptions of the remaining SFRs are included in the sections of the datasheet associated with their corresponding system function. SFR Definition 12.1. DPL: Data Pointer Low Byte Bit Name Type Reset 0 0 0 0 7 6 5 4 DPL[7:0] R/W 0 0 0 0 3 2 1 0 SFR Address = 0x82 Bit Name 7:0 DPL[7:0] Data Pointer Low. Function The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indirectly addressed Flash memory or XRAM. SFR Definition 12.2. DPH: Data Pointer High Byte Bit Name Type Reset 0 0 0 0 7 6 5 4 DPH[7:0] R/W 0 0 0 0 3 2 1 0 SFR Address = 0x83 Bit Name 7:0 DPH[7:0] Data Pointer High. Function The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indirectly addressed Flash memory or XRAM. 78 Rev. 0.2 C8051F336/7/8/9 SFR Definition 12.3. SP: Stack Pointer Bit Name Type Reset 0 0 0 0 7 6 5 4 SP[7:0] R/W 0 1 1 1 3 2 1 0 SFR Address = 0x81 Bit Name 7:0 SP[7:0] Stack Pointer. Function The Stack Pointer holds the location of the top of the stack. The stack pointer is incremented before every PUSH operation. The SP register defaults to 0x07 after reset. SFR Definition 12.4. ACC: Accumulator Bit Name Type Reset 0 0 0 0 7 6 5 4 ACC[7:0] R/W 0 0 0 0 3 2 1 0 SFR Address = 0xE0; Bit-Addressable Bit Name 7:0 ACC[7:0] Accumulator. Function This register is the accumulator for arithmetic operations. SFR Definition 12.5. B: B Register Bit Name Type Reset 0 0 0 0 7 6 5 4 B[7:0] R/W 0 0 0 0 3 2 1 0 SFR Address = 0xF0; Bit-Addressable Bit Name 7:0 B[7:0] B Register. Function This register serves as a second accumulator for certain arithmetic operations. Rev. 0.2 79 C8051F336/7/8/9 SFR Definition 12.6. PSW: Program Status Word Bit Name Type Reset 7 CY R/W 0 6 AC R/W 0 5 F0 R/W 0 0 4 RS[1:0] R/W 0 3 2 OV R/W 0 1 F1 R/W 0 0 PARITY R 0 SFR Address = 0xD0; Bit-Addressable Bit Name 7 CY Carry Flag. Function This bit is set when the last arithmetic operation resulted in a carry (addition) or a borrow (subtraction). It is cleared to logic 0 by all other arithmetic operations. 6 AC Auxiliary Carry Flag. This bit is set when the last arithmetic operation resulted in a carry into (addition) or a borrow from (subtraction) the high order nibble. It is cleared to logic 0 by all other arithmetic operations. 5 4:3 F0 RS[1:0] User Flag 0. This is a bit-addressable, general purpose flag for use under software control. Register Bank Select. These bits select which register bank is used during register accesses. 00: Bank 0, Addresses 0x00-0x07 01: Bank 1, Addresses 0x08-0x0F 10: Bank 2, Addresses 0x10-0x17 11: Bank 3, Addresses 0x18-0x1F 2 OV Overflow Flag. This bit is set to 1 under the following circumstances: * An ADD, ADDC, or SUBB instruction causes a sign-change overflow. * A MUL instruction results in an overflow (result is greater than 255). * A DIV instruction causes a divide-by-zero condition. The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all other cases. 1 0 F1 PARITY User Flag 1. This is a bit-addressable, general purpose flag for use under software control. Parity Flag. This bit is set to logic 1 if the sum of the eight bits in the accumulator is odd and cleared if the sum is even. 80 Rev. 0.2 C8051F336/7/8/9 13. Memory Organization The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are two separate memory spaces: program memory and data memory. Program and data memory share the same address space but are accessed via different instruction types. The memory organization of the C8051F336/7/8/9 device family is shown in Figure 13.1 PROGRAM/DATA MEMORY (FLASH) 0xFF 0x3E00 0x3DFF RESERVED 0x80 0x7F 16 K FLASH (In-System Programmable in 512 Byte Sectors) 0x30 0x2F 0x20 0x1F 0x00 0x0000 DATA MEMORY (RAM) INTERNAL DATA ADDRESS SPACE Upper 128 RAM (Indirect Addressing Only) (Direct and Indirect Addressing) Bit Addressable General Purpose Registers Special Function Register's (Direct Addressing Only) Lower 128 RAM (Direct and Indirect Addressing) EXTERNAL DATA ADDRESS SPACE 0xFFFF Same 512 bytes as from 0x0000 to 0x01FF, wrapped on 512-byte boundaries 0x0200 0x01FF 0x0000 XRAM - 512 Bytes (accessable using MOVX instruction) Figure 13.1. C8051F336/7/8/9 Memory Map Rev. 0.2 81 C8051F336/7/8/9 13.1. Program Memory The CIP-51 core has a 64 kB program memory space. The C8051F336/7/8/9 implements 16 kB of this program memory space as in-system, re-programmable Flash memory, organized in a contiguous block from addresses 0x0000 to 0x3DFF. The address 0x3DFF serves as the security lock byte for the device, and addresses above 0x3DFF are reserved. 0x3FFF Reserved Area 0x3E00 0x3DFE Lock Byte Page 0x3C00 Flash Memory Space 0x0000 Figure 13.2. Flash Program Memory Map 13.1.1. MOVX Instruction and Program Memory The MOVX instruction in an 8051 device is typically used to access external data memory. On the C8051F336/7/8/9 devices, the MOVX instruction is normally used to read and write on-chip XRAM, but can be re-configured to write and erase on-chip Flash memory space. MOVC instructions are always used to read Flash memory, while MOVX write instructions are used to erase and write Flash. This Flash access feature provides a mechanism for the C8051F336/7/8/9 to update program code and use the program memory space for non-volatile data storage. Refer to Section "16. Flash Memory" on page 98 for further details. 82 Rev. 0.2 FLASH memory organized in 512-byte pages Lock Byte 0x3DFF C8051F336/7/8/9 13.2. Data Memory The C8051F336/7/8/9 device family includes 768 bytes of RAM data memory. 256 bytes of this memory is mapped into the internal RAM space of the 8051. 512 bytes of this memory is on-chip "external" memory. The data memory map is shown in Figure 13.1 for reference. 13.2.1. Internal RAM There are 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either direct or indirect addressing may be used to access the lower 128 bytes of data memory. Locations 0x00 through 0x1F are addressable as four banks of general purpose registers, each bank consisting of eight byte-wide registers. The next 16 bytes, locations 0x20 through 0x2F, may either be addressed as bytes or as 128 bit locations accessible with the direct addressing mode. The upper 128 bytes of data memory are accessible only by indirect addressing. This region occupies the same address space as the Special Function Registers (SFR) but is physically separate from the SFR space. The addressing mode used by an instruction when accessing locations above 0x7F determines whether the CPU accesses the upper 128 bytes of data memory space or the SFRs. Instructions that use direct addressing will access the SFR space. Instructions using indirect addressing above 0x7F access the upper 128 bytes of data memory. Figure 13.1 illustrates the data memory organization of the C8051F336/7/8/9. 13.2.1.1.General Purpose Registers The lower 32 bytes of data memory, locations 0x00 through 0x1F, may be addressed as four banks of general-purpose registers. Each bank consists of eight byte-wide registers designated R0 through R7. Only one of these banks may be enabled at a time. Two bits in the program status word, RS0 (PSW.3) and RS1 (PSW.4), select the active register bank (see description of the PSW in SFR Definition 12.6). This allows fast context switching when entering subroutines and interrupt service routines. Indirect addressing modes use registers R0 and R1 as index registers. 13.2.1.2.Bit Addressable Locations In addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20 through 0x2F are also accessible as 128 individually addressable bits. Each bit has a bit address from 0x00 to 0x7F. Bit 0 of the byte at 0x20 has bit address 0x00 while bit7 of the byte at 0x20 has bit address 0x07. Bit 7 of the byte at 0x2F has bit address 0x7F. A bit access is distinguished from a full byte access by the type of instruction used (bit source or destination operands as opposed to a byte source or destination). The MCS-51TM assembly language allows an alternate notation for bit addressing of the form XX.B where XX is the byte address and B is the bit position within the byte. For example, the instruction: MOV C, 22.3h moves the Boolean value at 0x13 (bit 3 of the byte at location 0x22) into the Carry flag. Rev. 0.2 83 C8051F336/7/8/9 13.2.1.3.Stack A programmer's stack can be located anywhere in the 256-byte data memory. The stack area is designated using the Stack Pointer (SP) SFR. The SP will point to the last location used. The next value pushed on the stack is placed at SP+1 and then SP is incremented. A reset initializes the stack pointer to location 0x07. Therefore, the first value pushed on the stack is placed at location 0x08, which is also the first register (R0) of register bank 1. Thus, if more than one register bank is to be used, the SP should be initialized to a location in the data memory not being used for data storage. The stack depth can extend up to 256 bytes. 13.2.2. External RAM There are 512 bytes of on-chip RAM mapped into the external data memory space. All of these address locations may be accessed using the external move instruction (MOVX) and the data pointer (DPTR), or using MOVX indirect addressing mode. If the MOVX instruction is used with an 8-bit address operand (such as @R1), then the high byte of the 16-bit address is provided by the External Memory Interface Control Register (EMI0CN as shown in SFR Definition 13.1). Note: the MOVX instruction is also used for writes to the Flash memory. See Section "16. Flash Memory" on page 98 for details. The MOVX instruction accesses XRAM by default. For a 16-bit MOVX operation (@DPTR), the upper 7 bits of the 16-bit external data memory address word are "don't cares". As a result, the 512-byte RAM is mapped modulo style over the entire 64 k external data memory address range. For example, the XRAM byte at address 0x0000 is shadowed at addresses 0x0200, 0x0400, 0x0600, 0x0800, etc. This is a useful feature when performing a linear memory fill, as the address pointer doesn't have to be reset when reaching the RAM block boundary. SFR Definition 13.1. EMI0CN: External Memory Interface Control Bit Name Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 PGSEL R/W 0 SFR Address = 0xAA Bit Name 7:1 0 UNUSED PGSEL Function Unused. Read = 0000000b; Write = Don't Care XRAM Page Select. The EMI0CN register provides the high byte of the 16-bit external data memory address when using an 8-bit MOVX command, effectively selecting a 256-byte page of RAM. Since the upper (unused) bits of the register are always zero, the PGSEL determines which page of XRAM is accessed. For Example: If EMI0CN = 0x01, addresses 0x0100 through 0x01FF will be accessed. 84 Rev. 0.2 C8051F336/7/8/9 14. Special Function Registers The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers (SFRs). The SFRs provide control and data exchange with the C8051F336/7/8/9's resources and peripherals. The CIP-51 controller core duplicates the SFRs found in a typical 8051 implementation as well as implementing additional SFRs used to configure and access the sub-systems unique to the C8051F336/7/8/9. This allows the addition of new functionality while retaining compatibility with the MCS51TM instruction set. Table 14.1 lists the SFRs implemented in the C8051F336/7/8/9 device family. The SFR registers are accessed anytime the direct addressing mode is used to access memory locations from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, SCON0, IE, etc.) are bitaddressable as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied addresses in the SFR space are reserved for future use. Accessing these areas will have an indeterminate effect and should be avoided. Refer to the corresponding pages of the data sheet, as indicated in Table 14.2, for a detailed description of each register. Table 14.1. Special Function Register (SFR) Memory Map F8 F0 E8 E0 D8 D0 C8 C0 B8 B0 A8 A0 98 90 88 80 SPI0CN PCA0L PCA0H PCA0CPL0 PCA0CPH0 P0MAT P0MASK VDM0CN B P0MDIN P1MDIN P2MDIN EIP1 PCA0PWM ADC0CN PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2 P1MAT P1MASK RSTSRC ACC XBR0 XBR1 OSCLCN IT01CF EIE1 SMB0ADM PCA0CN PCA0MD PCA0CPM0 PCA0CPM1 PCA0CPM2 PSW REF0CN P0SKIP P1SKIP P2SKIP SMB0ADR TMR2CN TMR2RLL TMR2RLH TMR2L TMR2H SMB0CN SMB0CF SMB0DAT ADC0GTL ADC0GTH ADC0LTL ADC0LTH IP IDA0CN AMX0N AMX0P ADC0CF ADC0L ADC0H OSCXCN OSCICN OSCICL FLSCL FLKEY IE CLKSEL EMI0CN P2 SPI0CFG SPI0CKR SPI0DAT P0MDOUT P1MDOUT P2MDOUT SCON0 SBUF0 CPT0CN CPT0MD CPT0MX P1 TMR3CN TMR3RLL TMR3RLH TMR3L TMR3H IDA0L IDA0H TCON TMOD TL0 TL1 TH0 TH1 CKCON PSCTL P0 SP DPL DPH PCON 0(8) 1(9) 2(A) 3(B) 4(C) 5(D) 6(E) 7(F) (bit addressable) Rev. 0.2 85 C8051F336/7/8/9 Table 14.2. Special Function Registers SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register ACC ADC0CF ADC0CN ADC0GTH ADC0GTL ADC0H ADC0L ADC0LTH ADC0LTL AMX0N AMX0P B CKCON CLKSEL CPT0CN CPT0MD CPT0MX DPH DPL EIE1 EIP1 EMI0CN FLKEY FLSCL IDA0CN IDA0H IDA0L IE IP IT01CF OSCICL OSCICN OSCLCN Address 0xE0 0xBC 0xE8 0xC4 0xC3 0xBE 0xBD 0xC6 0xC5 0xBA 0xBB 0xF0 0x8E 0xA9 0x9B 0x9D 0x9F 0x83 0x82 0xE6 0xF6 0xAA 0xB7 0xB6 0xB9 0x97 0x96 0xA8 0xB8 0xE4 0xB3 0xB2 0xE3 Accumulator ADC0 Configuration ADC0 Control ADC0 Greater-Than Compare High ADC0 Greater-Than Compare Low ADC0 High ADC0 Low ADC0 Less-Than Compare Word High ADC0 Less-Than Compare Word Low AMUX0 Negative Channel Select AMUX0 Positive Channel Select B Register Clock Control Clock Select Comparator0 Control Comparator0 Mode Selection Comparator0 MUX Selection Data Pointer High Data Pointer Low Extended Interrupt Enable 1 Extended Interrupt Priority 1 External Memory Interface Control Flash Lock and Key Flash Scale Current Mode DAC0 Control Current Mode DAC0 High Current Mode DAC0 Low Interrupt Enable Interrupt Priority INT0/INT1 Configuration Internal Oscillator Calibration Internal Oscillator Control Low-Frequency Oscillator Control Description Page 79 48 50 51 51 49 49 52 52 57 56 79 188 117 68 69 71 78 78 94 95 84 105 106 61 62 62 92 93 97 118 119 120 86 Rev. 0.2 C8051F336/7/8/9 Table 14.2. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register OSCXCN P0 P0MASK P0MAT P0MDIN P0MDOUT P0SKIP P1 P1MASK P1MAT P1MDIN P1MDOUT P1SKIP P2 P2MDIN P2MDOUT P2SKIP PCA0CN PCA0CPH0 PCA0CPH1 PCA0CPH2 PCA0CPL0 PCA0CPL1 PCA0CPL2 PCA0CPM0 PCA0CPM1 PCA0CPM2 PCA0H PCA0L PCA0MD PCA0PWM PCON PSCTL PSW Address 0xB1 0x80 0xFE 0xFD 0xF1 0xA4 0xD4 0x90 0xEE 0xED 0xF2 0xA5 0xD5 0xA0 0xF3 0xA6 0xD6 0xD8 0xFC 0xEA 0xEC 0xFB 0xE9 0xEB 0xDA 0xDB 0xDC 0xFA 0xF9 0xD9 0xF7 0x87 0x8F 0xD0 Port 0 Latch Port 0 Mask Configuration Port 0 Match Configuration Port 0 Input Mode Configuration Port 0 Output Mode Configuration Port 0 Skip Port 1 Latch Port 1Mask Configuration Port 1 Match Configuration Port 1 Input Mode Configuration Port 1 Output Mode Configuration Port 1 Skip Port 2 Latch Port 2 Input Mode Configuration Port 2 Output Mode Configuration Port 2 Skip PCA Control PCA Capture 0 High PCA Capture 1 High PCA Capture 2 High PCA Capture 0 Low PCA Capture 1 Low PCA Capture 2 Low PCA Module 0 Mode Register PCA Module 1 Mode Register PCA Module 2 Mode Register PCA Counter High PCA Counter Low PCA Mode PCA PWM Configuration Power Control Program Store R/W Control Program Status Word Description External Oscillator Control Page 122 138 136 136 139 139 140 140 137 137 141 141 142 142 143 143 144 223 228 228 228 228 228 228 226 226 226 227 227 224 225 109 104 80 Rev. 0.2 87 C8051F336/7/8/9 Table 14.2. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register REF0CN RSTSRC SBUF0 SCON0 SMB0ADM SMB0ADR SMB0CF SMB0CN SMB0DAT SP SPI0CFG SPI0CKR SPI0CN SPI0DAT TCON TH0 TH1 TL0 TL1 TMOD TMR2CN TMR2H TMR2L TMR2RLH TMR2RLL TMR3CN TMR3H TMR3L TMR3RLH TMR3RLL VDM0CN XBR0 XBR1 Address 0xD1 0xEF 0x99 0x98 0xE7 0xD7 0xC1 0xC0 0xC2 0x81 0xA1 0xA2 0xF8 0xA3 0x88 0x8C 0x8D 0x8A 0x8B 0x89 0xC8 0xCD 0xCC 0xCB 0xCA 0x91 0x95 0x94 0x93 0x92 0xFF 0xE1 0xE2 Description Voltage Reference Control Reset Source Configuration/Status UART0 Data Buffer UART0 Control SMBus Slave Address Mask SMBus Slave Address SMBus Configuration SMBus Control SMBus Data Stack Pointer SPI Configuration SPI Clock Rate Control SPI Control SPI Data Timer/Counter Control Timer/Counter 0 High Timer/Counter 1 High Timer/Counter 0 Low Timer/Counter 1 Low Timer/Counter Mode Timer/Counter 2 Control Timer/Counter 2 High Timer/Counter 2 Low Timer/Counter 2 Reload High Timer/Counter 2 Reload Low Timer/Counter 3Control Timer/Counter 3 High Timer/Counter 3Low Timer/Counter 3 Reload High Timer/Counter 3 Reload Low VDD Monitor Control Port I/O Crossbar Control 0 Port I/O Crossbar Control 1 Page 64 115 172 171 156 156 151 153 157 79 181 183 182 183 193 196 196 195 195 194 200 202 201 201 201 206 208 207 207 207 113 134 135 88 Rev. 0.2 C8051F336/7/8/9 15. Interrupts The C8051F336/7/8/9 includes an extended interrupt system supporting a total of 14 interrupt sources with two priority levels. The allocation of interrupt sources between on-chip peripherals and external input pins varies according to the specific version of the device. Each interrupt source has one or more associated interrupt-pending flag(s) located in an SFR. When a peripheral or external source meets a valid interrupt condition, the associated interrupt-pending flag is set to logic 1. If interrupts are enabled for the source, an interrupt request is generated when the interrupt-pending flag is set. As soon as execution of the current instruction is complete, the CPU generates an LCALL to a predetermined address to begin execution of an interrupt service routine (ISR). Each ISR must end with an RETI instruction, which returns program execution to the next instruction that would have been executed if the interrupt request had not occurred. If interrupts are not enabled, the interrupt-pending flag is ignored by the hardware and program execution continues as normal. (The interrupt-pending flag is set to logic 1 regardless of the interrupt's enable/disable state.) Each interrupt source can be individually enabled or disabled through the use of an associated interrupt enable bit in an SFR (IE-EIE1). However, interrupts must first be globally enabled by setting the EA bit (IE.7) to logic 1 before the individual interrupt enables are recognized. Setting the EA bit to logic 0 disables all interrupt sources regardless of the individual interrupt-enable settings. Note: Any instruction that clears a bit to disable an interrupt should be immediately followed by an instruction that has two or more opcode bytes. Using EA (global interrupt enable) as an example: // in 'C': EA = 0; // clear EA bit. EA = 0; // this is a dummy instruction with two-byte opcode. ; in assembly: CLR EA ; clear EA bit. CLR EA ; this is a dummy instruction with two-byte opcode. For example, if an interrupt is posted during the execution phase of a "CLR EA" opcode (or any instruction which clears a bit to disable an interrupt source), and the instruction is followed by a single-cycle instruction, the interrupt may be taken. However, a read of the enable bit will return a '0' inside the interrupt service routine. When the bit-clearing opcode is followed by a multi-cycle instruction, the interrupt will not be taken. Some interrupt-pending flags are automatically cleared by the hardware when the CPU vectors to the ISR. However, most are not cleared by the hardware and must be cleared by software before returning from the ISR. If an interrupt-pending flag remains set after the CPU completes the return-from-interrupt (RETI) instruction, a new interrupt request will be generated immediately and the CPU will re-enter the ISR after the completion of the next instruction. Rev. 0.2 89 C8051F336/7/8/9 15.1. MCU Interrupt Sources and Vectors The C8051F336/7/8/9 MCUs support 14 interrupt sources. Software can simulate an interrupt by setting any interrupt-pending flag to logic 1. If interrupts are enabled for the flag, an interrupt request will be generated and the CPU will vector to the ISR address associated with the interrupt-pending flag. MCU interrupt sources, associated vector addresses, priority order and control bits are summarized in Table 15.1. Refer to the datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). 15.1.1. Interrupt Priorities Each interrupt source can be individually programmed to one of two priority levels: low or high. A low priority interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be preempted. Each interrupt has an associated interrupt priority bit in an SFR (IP or EIP1) used to configure its priority level. Low priority is the default. If two interrupts are recognized simultaneously, the interrupt with the higher priority is serviced first. If both interrupts have the same priority level, a fixed priority order is used to arbitrate, given in Table 15.1. 15.1.2. Interrupt Latency Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are sampled and priority decoded each system clock cycle. Therefore, the fastest possible response time is 5 system clock cycles: 1 clock cycle to detect the interrupt and 4 clock cycles to complete the LCALL to the ISR. If an interrupt is pending when a RETI is executed, a single instruction is executed before an LCALL is made to service the pending interrupt. Therefore, the maximum response time for an interrupt (when no other interrupt is currently being serviced or the new interrupt is of greater priority) occurs when the CPU is performing an RETI instruction followed by a DIV as the next instruction. In this case, the response time is 18 system clock cycles: 1 clock cycle to detect the interrupt, 5 clock cycles to execute the RETI, 8 clock cycles to complete the DIV instruction and 4 clock cycles to execute the LCALL to the ISR. If the CPU is executing an ISR for an interrupt with equal or higher priority, the new interrupt will not be serviced until the current ISR completes, including the RETI and following instruction. 90 Rev. 0.2 C8051F336/7/8/9 Table 15.1. Interrupt Summary Cleared by HW? Interrupt Source Interrupt Vector Priority Order Pending Flag Bit addressable? Enable Flag Priority Control Reset External Interrupt 0 (/INT0) Timer 0 Overflow External Interrupt 1 (/INT1) Timer 1 Overflow UART0 Timer 2 Overflow 0x0000 0x0003 0x000B 0x0013 0x001B 0x0023 0x002B Top 0 1 2 3 4 5 None IE0 (TCON.1) TF0 (TCON.5) IE1 (TCON.3) TF1 (TCON.7) RI0 (SCON0.0) TI0 (SCON0.1) TF2H (TMR2CN.7) TF2L (TMR2CN.6) SPIF (SPI0CN.7) WCOL (SPI0CN.6) MODF (SPI0CN.5) RXOVRN (SPI0CN.4) SI (SMB0CN.0) None AD0WINT (ADC0CN.3) AD0INT (ADC0CN.5) CF (PCA0CN.7) CCFn (PCA0CN.n) COVF (PCA0PWM.6) CP0FIF (CPT0CN.4) CP0RIF (CPT0CN.5) N/A TF3H (TMR3CN.7) TF3L (TMR3CN.6) N/A N/A Y Y Y Y Y Y Y Y Y Y N N Always Enabled Always Highest EX0 (IE.0) PX0 (IP.0) ET0 (IE.1) PT0 (IP.1) EX1 (IE.2) PX1 (IP.2) ET1 (IE.3) PT1 (IP.3) ES0 (IE.4) PS0 (IP.4) ET2 (IE.5) PT2 (IP.5) ESPI0 (IE.6) PSPI0 (IP.6) PSMB0 (EIP1.0) PMAT (EIP1.1) PWADC0 (EIP1.2) PADC0 (EIP1.3) PPCA0 (EIP1.4) PCP0 (EIP1.5) N/A PT3 (EIP1.7) SPI0 0x0033 6 Y N SMB0 Port Match ADC0 Window Compare ADC0 Conversion Complete Programmable Counter Array Comparator0 RESERVED Timer 3 Overflow 0x003B 0x0043 0x004B 0x0053 0x005B 0x0063 0x006B 0x0073 7 8 9 10 11 12 13 14 ESMB0 (EIE1.0) EMAT N/A N/A (EIE1.1) EWADC0 Y N (EIE1.2) EADC0 Y N (EIE1.3) Y N Y N N N EPCA0 (EIE1.4) ECP0 (EIE1.5) N/A N/A N/A ET3 N N (EIE1.7) 15.2. Interrupt Register Descriptions The SFRs used to enable the interrupt sources and set their priority level are described in this section. Refer to the data sheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). Rev. 0.2 91 C8051F336/7/8/9 SFR Definition 15.1. IE: Interrupt Enable Bit Name Type Reset 7 EA R/W 0 6 ESPI0 R/W 0 5 ET2 R/W 0 4 ES0 R/W 0 3 ET1 R/W 0 2 EX1 R/W 0 1 ET0 R/W 0 0 EX0 R/W 0 SFR Address = 0xA8; Bit-Addressable Bit Name 7 EA Function Enable All Interrupts. Globally enables/disables all interrupts. It overrides individual interrupt mask settings. 0: Disable all interrupt sources. 1: Enable each interrupt according to its individual mask setting. Enable Serial Peripheral Interface (SPI0) Interrupt. This bit sets the masking of the SPI0 interrupts. 0: Disable all SPI0 interrupts. 1: Enable interrupt requests generated by SPI0. Enable Timer 2 Interrupt. This bit sets the masking of the Timer 2 interrupt. 0: Disable Timer 2 interrupt. 1: Enable interrupt requests generated by the TF2L or TF2H flags. Enable UART0 Interrupt. This bit sets the masking of the UART0 interrupt. 0: Disable UART0 interrupt. 1: Enable UART0 interrupt. Enable Timer 1 Interrupt. This bit sets the masking of the Timer 1 interrupt. 0: Disable all Timer 1 interrupt. 1: Enable interrupt requests generated by the TF1 flag. Enable External Interrupt 1. This bit sets the masking of External Interrupt 1. 0: Disable external interrupt 1. 1: Enable interrupt requests generated by the /INT1 input. Enable Timer 0 Interrupt. This bit sets the masking of the Timer 0 interrupt. 0: Disable all Timer 0 interrupt. 1: Enable interrupt requests generated by the TF0 flag. Enable External Interrupt 0. This bit sets the masking of External Interrupt 0. 0: Disable external interrupt 0. 1: Enable interrupt requests generated by the /INT0 input. 6 ESPI0 5 ET2 4 ES0 3 ET1 2 EX1 1 ET0 0 EX0 92 Rev. 0.2 C8051F336/7/8/9 SFR Definition 15.2. IP: Interrupt Priority Bit Name Type Reset R 1 7 6 PSPI0 R/W 0 5 PT2 R/W 0 4 PS0 R/W 0 3 PT1 R/W 0 2 PX1 R/W 0 1 PT0 R/W 0 0 PX0 R/W 0 SFR Address = 0xB8; Bit-Addressable Bit Name 7 6 Function UNUSED Unused. Read = 1, Write = Don't Care. PSPI0 Serial Peripheral Interface (SPI0) Interrupt Priority Control. This bit sets the priority of the SPI0 interrupt. 0: SPI0 interrupt set to low priority level. 1: SPI0 interrupt set to high priority level. Timer 2 Interrupt Priority Control. This bit sets the priority of the Timer 2 interrupt. 0: Timer 2 interrupt set to low priority level. 1: Timer 2 interrupt set to high priority level. UART0 Interrupt Priority Control. This bit sets the priority of the UART0 interrupt. 0: UART0 interrupt set to low priority level. 1: UART0 interrupt set to high priority level. Timer 1 Interrupt Priority Control. This bit sets the priority of the Timer 1 interrupt. 0: Timer 1 interrupt set to low priority level. 1: Timer 1 interrupt set to high priority level. External Interrupt 1 Priority Control. This bit sets the priority of the External Interrupt 1 interrupt. 0: External Interrupt 1 set to low priority level. 1: External Interrupt 1 set to high priority level. Timer 0 Interrupt Priority Control. This bit sets the priority of the Timer 0 interrupt. 0: Timer 0 interrupt set to low priority level. 1: Timer 0 interrupt set to high priority level. External Interrupt 0 Priority Control. This bit sets the priority of the External Interrupt 0 interrupt. 0: External Interrupt 0 set to low priority level. 1: External Interrupt 0 set to high priority level. 5 PT2 4 PS0 3 PT1 2 PX1 1 PT0 0 PX0 Rev. 0.2 93 C8051F336/7/8/9 SFR Definition 15.3. EIE1: Extended Interrupt Enable 1 Bit Name Type Reset 7 ET3 R/W 0 6 Reserved R/W 0 5 ECP0 R/W 0 4 EPCA0 R/W 0 3 EADC0 R/W 0 2 EWADC0 R/W 0 1 EMAT R/W 0 0 ESMB0 R/W 0 SFR Address = 0xE6 Bit Name 7 ET3 Function Enable Timer 3 Interrupt. This bit sets the masking of the Timer 3 interrupt. 0: Disable Timer 3 interrupts. 1: Enable interrupt requests generated by the TF3L or TF3H flags. 6 5 Reserved Reserved. Must Write 0. ECP0 Enable Comparator0 (CP0) Interrupt. This bit sets the masking of the CP0 interrupt. 0: Disable CP0 interrupts. 1: Enable interrupt requests generated by the CP0RIF or CP0FIF flags. Enable Programmable Counter Array (PCA0) Interrupt. This bit sets the masking of the PCA0 interrupts. 0: Disable all PCA0 interrupts. 1: Enable interrupt requests generated by PCA0. Enable ADC0 Conversion Complete Interrupt. This bit sets the masking of the ADC0 Conversion Complete interrupt. 0: Disable ADC0 Conversion Complete interrupt. 1: Enable interrupt requests generated by the AD0INT flag. 4 EPCA0 3 EADC0 2 EWADC0 Enable Window Comparison ADC0 Interrupt. This bit sets the masking of ADC0 Window Comparison interrupt. 0: Disable ADC0 Window Comparison interrupt. 1: Enable interrupt requests generated by ADC0 Window Compare flag (AD0WINT). EMAT Enable Port Match Interrupts. This bit sets the masking of the Port Match Event interrupt. 0: Disable all Port Match interrupts. 1: Enable interrupt requests generated by a Port Match. Enable SMBus (SMB0) Interrupt. This bit sets the masking of the SMB0 interrupt. 0: Disable all SMB0 interrupts. 1: Enable interrupt requests generated by SMB0. 1 0 ESMB0 94 Rev. 0.2 C8051F336/7/8/9 SFR Definition 15.4. EIP1: Extended Interrupt Priority 1 Bit Name Type Reset 7 PT3 R/W 0 6 Reserved R/W 0 5 PCP0 R/W 0 4 PPCA0 R/W 0 3 PADC0 R/W 0 2 PWADC0 R/W 0 1 PMAT R/W 0 0 PSMB0 R/W 0 SFR Address = 0xF6 Bit Name 7 PT3 Function Timer 3 Interrupt Priority Control. This bit sets the priority of the Timer 3 interrupt. 0: Timer 3 interrupts set to low priority level. 1: Timer 3 interrupts set to high priority level. 6 5 Reserved Reserved. Must Write 0. PCP0 Comparator0 (CP0) Interrupt Priority Control. This bit sets the priority of the CP0 interrupt. 0: CP0 interrupt set to low priority level. 1: CP0 interrupt set to high priority level. Programmable Counter Array (PCA0) Interrupt Priority Control. This bit sets the priority of the PCA0 interrupt. 0: PCA0 interrupt set to low priority level. 1: PCA0 interrupt set to high priority level. ADC0 Conversion Complete Interrupt Priority Control. This bit sets the priority of the ADC0 Conversion Complete interrupt. 0: ADC0 Conversion Complete interrupt set to low priority level. 1: ADC0 Conversion Complete interrupt set to high priority level. 4 PPCA0 3 PADC0 2 PWADC0 ADC0 Window Comparator Interrupt Priority Control. This bit sets the priority of the ADC0 Window interrupt. 0: ADC0 Window interrupt set to low priority level. 1: ADC0 Window interrupt set to high priority level. PMAT Port Match Interrupt Priority Control. This bit sets the priority of the Port Match Event interrupt. 0: Port Match interrupt set to low priority level. 1: Port Match interrupt set to high priority level. SMBus (SMB0) Interrupt Priority Control. This bit sets the priority of the SMB0 interrupt. 0: SMB0 interrupt set to low priority level. 1: SMB0 interrupt set to high priority level. 1 0 PSMB0 Rev. 0.2 95 C8051F336/7/8/9 15.3. External Interrupts /INT0 and /INT1 The /INT0 and /INT1 external interrupt sources are configurable as active high or low, edge or level sensitive. The IN0PL (/INT0 Polarity) and IN1PL (/INT1 Polarity) bits in the IT01CF register select active high or active low; the IT0 and IT1 bits in TCON (Section "24.1. Timer 0 and Timer 1" on page 189) select level or edge sensitive. The table below lists the possible configurations. IT0 1 1 0 0 IN0PL 0 1 0 1 /INT0 Interrupt Active low, edge sensitive Active high, edge sensitive Active low, level sensitive Active high, level sensitive IT1 1 1 0 0 IN1PL 0 1 0 1 /INT1 Interrupt Active low, edge sensitive Active high, edge sensitive Active low, level sensitive Active high, level sensitive /INT0 and /INT1 are assigned to Port pins as defined in the IT01CF register (see SFR Definition 15.5). Note that /INT0 and /INT0 Port pin assignments are independent of any Crossbar assignments. /INT0 and /INT1 will monitor their assigned Port pins without disturbing the peripheral that was assigned the Port pin via the Crossbar. To assign a Port pin only to /INT0 and/or /INT1, configure the Crossbar to skip the selected pin(s). This is accomplished by setting the associated bit in register XBR0 (see Section "20.3. Priority Crossbar Decoder" on page 131 for complete details on configuring the Crossbar). IE0 (TCON.1) and IE1 (TCON.3) serve as the interrupt-pending flags for the /INT0 and /INT1 external interrupts, respectively. If an /INT0 or /INT1 external interrupt is configured as edge-sensitive, the corresponding interrupt-pending flag is automatically cleared by the hardware when the CPU vectors to the ISR. When configured as level sensitive, the interrupt-pending flag remains logic 1 while the input is active as defined by the corresponding polarity bit (IN0PL or IN1PL); the flag remains logic 0 while the input is inactive. The external interrupt source must hold the input active until the interrupt request is recognized. It must then deactivate the interrupt request before execution of the ISR completes or another interrupt request will be generated. 96 Rev. 0.2 C8051F336/7/8/9 SFR Definition 15.5. IT01CF: INT0/INT1 Configuration Bit Name Type Reset 7 IN1PL R/W 0 0 6 5 IN1SL[2:0] R/W 0 0 4 3 IN0PL R/W 0 0 2 1 IN0SL[2:0] R/W 0 1 0 SFR Address = 0xE4 Bit Name 7 IN1PL /INT1 Polarity. 0: /INT1 input is active low. 1: /INT1 input is active high. Function 6:4 IN1SL[2:0] /INT1 Port Pin Selection Bits. These bits select which Port pin is assigned to /INT1. Note that this pin assignment is independent of the Crossbar; /INT1 will monitor the assigned Port pin without disturbing the peripheral that has been assigned the Port pin via the Crossbar. The Crossbar will not assign the Port pin to a peripheral if it is configured to skip the selected pin. 000: Select P0.0 001: Select P0.1 010: Select P0.2 011: Select P0.3 100: Select P0.4 101: Select P0.5 110: Select P0.6 111: Select P0.7 IN0PL /INT0 Polarity. 0: /INT0 input is active low. 1: /INT0 input is active high. 3 2:0 IN0SL[2:0] /INT0 Port Pin Selection Bits. These bits select which Port pin is assigned to /INT0. Note that this pin assignment is independent of the Crossbar; /INT0 will monitor the assigned Port pin without disturbing the peripheral that has been assigned the Port pin via the Crossbar. The Crossbar will not assign the Port pin to a peripheral if it is configured to skip the selected pin. 000: Select P0.0 001: Select P0.1 010: Select P0.2 011: Select P0.3 100: Select P0.4 101: Select P0.5 110: Select P0.6 111: Select P0.7 Rev. 0.2 97 C8051F336/7/8/9 16. Flash Memory On-chip, re-programmable Flash memory is included for program code and non-volatile data storage. The Flash memory can be programmed in-system, a single byte at a time, through the C2 interface or by software using the MOVX instruction. Once cleared to logic 0, a Flash bit must be erased to set it back to logic 1. Flash bytes would typically be erased (set to 0xFF) before being reprogrammed. The write and erase operations are automatically timed by hardware for proper execution; data polling to determine the end of the write/erase operation is not required. Code execution is stalled during a Flash write/erase operation. Refer to Table 6.5 for complete Flash memory electrical characteristics. 16.1. Programming The Flash Memory The simplest means of programming the Flash memory is through the C2 interface using programming tools provided by Silicon Labs or a third party vendor. This is the only means for programming a non-initialized device. For details on the C2 commands to program Flash memory, see Section "26. C2 Interface" on page 229. To ensure the integrity of Flash contents, it is strongly recommended that the on-chip VDD Monitor be enabled in any system that includes code that writes and/or erases Flash memory from software. See Section 16.4 for more details. 16.1.1. Flash Lock and Key Functions Flash writes and erases by user software are protected with a lock and key function. The Flash Lock and Key Register (FLKEY) must be written with the correct key codes, in sequence, before Flash operations may be performed. The key codes are: 0xA5, 0xF1. The timing does not matter, but the codes must be written in order. If the key codes are written out of order, or the wrong codes are written, Flash writes and erases will be disabled until the next system reset. Flash writes and erases will also be disabled if a Flash write or erase is attempted before the key codes have been written properly. The Flash lock resets after each write or erase; the key codes must be written again before a following Flash operation can be performed. The FLKEY register is detailed in SFR Definition 16.2. 16.1.2. Flash Erase Procedure The Flash memory can be programmed by software using the MOVX write instruction with the address and data byte to be programmed provided as normal operands. Before writing to Flash memory using MOVX, Flash write operations must be enabled by: (1) setting the PSWE Program Store Write Enable bit (PSCTL.0) to logic 1 (this directs the MOVX writes to target Flash memory); and (2) Writing the Flash key codes in sequence to the Flash Lock register (FLKEY). The PSWE bit remains set until cleared by software. A write to Flash memory can clear bits to logic 0 but cannot set them; only an erase operation can set bits to logic 1 in Flash. A byte location to be programmed should be erased before a new value is written. The Flash memory is organized in 512-byte pages. The erase operation applies to an entire page (setting all bytes in the page to 0xFF). To erase an entire 512-byte page, perform the following steps: Disable interrupts (recommended). Set thePSEE bit (register PSCTL). Set the PSWE bit (register PSCTL). Write the first key code to FLKEY: 0xA5. Write the second key code to FLKEY: 0xF1. Using the MOVX instruction, write a data byte to any location within the 512-byte page to be erased. Step 7. Clear the PSWE and PSEE bits. Step 1. Step 2. Step 3. Step 4. Step 5. Step 6. 98 Rev. 0.2 C8051F336/7/8/9 16.1.3. Flash Write Procedure Flash bytes are programmed by software with the following sequence: Step 1. Disable interrupts (recommended). Step 2. Erase the 512-byte Flash page containing the target location, as described in Section 16.1.2. Step 3. Set the PSWE bit (register PSCTL). Step 4. Clear the PSEE bit (register PSCTL). Step 5. Write the first key code to FLKEY: 0xA5. Step 6. Write the second key code to FLKEY: 0xF1. Step 7. Using the MOVX instruction, write a single data byte to the desired location within the 512byte sector. Step 8. Clear the PSWE bit. Steps 5-7 must be repeated for each byte to be written. After Flash writes are complete, PSWE should be cleared so that MOVX instructions do not target program memory. 16.2. Non-volatile Data Storage The Flash memory can be used for non-volatile data storage as well as program code. This allows data such as calibration coefficients to be calculated and stored at run time. Data is written using the MOVX write instruction and read using the MOVC instruction. Note: MOVX read instructions always target XRAM. Rev. 0.2 99 C8051F336/7/8/9 16.3. Security Options The CIP-51 provides security options to protect the Flash memory from inadvertent modification by software as well as to prevent the viewing of proprietary program code and constants. The Program Store Write Enable (bit PSWE in register PSCTL) and the Program Store Erase Enable (bit PSEE in register PSCTL) bits protect the Flash memory from accidental modification by software. PSWE must be explicitly set to `1' before software can modify the Flash memory; both PSWE and PSEE must be set to `1' before software can erase Flash memory. Additional security features prevent proprietary program code and data constants from being read or altered across the C2 interface. A Security Lock Byte located at the last byte of Flash user space offers protection of the Flash program memory from access (reads, writes, or erases) by unprotected code or the C2 interface. The Flash security mechanism allows the user to lock n 512-byte Flash pages, starting at page 0 (addresses 0x0000 to 0x01FF), where n is the 1's complement number represented by the Security Lock Byte. Note that the page containing the Flash Security Lock Byte is unlocked when no other Flash pages are locked (all bits of the Lock Byte are `1') and locked when any other Flash pages are locked (any bit of the Lock Byte is `0'). See example in Figure 16.1. Reserved Area Locked when any other FLASH pages are locked Lock Byte Lock Byte Page Unlocked FLASH Pages Access limit set according to the FLASH security lock byte Locked Flash Pages Security Lock Byte: 1s Complement: Flash pages locked: 11111101b 00000010b 3 (First two Flash pages + Lock Byte Page) Figure 16.1. Flash Program Memory Map 100 Rev. 0.2 C8051F336/7/8/9 The level of Flash security depends on the Flash access method. The three Flash access methods that can be restricted are reads, writes, and erases from the C2 debug interface, user firmware executing on unlocked pages, and user firmware executing on locked pages. Table 16.1 summarizes the Flash security features of the C8051F336/7/8/9 devices. Table 16.1. Flash Security Summary Action C2 Debug Interface Permitted Not Permitted Permitted Not Permitted Permitted Not Permitted Permitted C2 Device Erase Only Not Permitted Not Permitted Not Permitted User Firmware executing from: an unlocked page Permitted Flash Error Reset Permitted Flash Error Reset Permitted Flash Error Reset a locked page Permitted Permitted Permitted Permitted Permitted Permitted Read, Write or Erase unlocked pages (except page with Lock Byte) Read, Write or Erase locked pages (except page with Lock Byte) Read or Write page containing Lock Byte (if no pages are locked) Read or Write page containing Lock Byte (if any page is locked) Read contents of Lock Byte (if no pages are locked) Read contents of Lock Byte (if any page is locked) Erase page containing Lock Byte (if no pages are locked) Erase page containing Lock Byte--Unlock all pages (if any page is locked) Lock additional pages (change '1's to '0's in the Lock Byte) Unlock individual pages (change '0's to '1's in the Lock Byte) Read, Write or Erase Reserved Area Flash Error Reset Flash Error Reset Flash Error Reset Flash Error Reset Flash Error Reset Flash Error Reset Flash Error Reset Flash Error Reset Flash Error Reset Flash Error Reset C2 Device Erase - Erases all Flash pages including the page containing the Lock Byte. Flash Error Reset - Not permitted; Causes Flash Error Device Reset (FERROR bit in RSTSRC is '1' after reset). - All prohibited operations that are performed via the C2 interface are ignored (do not cause device reset). - Locking any Flash page also locks the page containing the Lock Byte. - Once written to, the Lock Byte cannot be modified except by performing a C2 Device Erase. - If user code writes to the Lock Byte, the Lock does not take effect until the next device reset. Rev. 0.2 101 C8051F336/7/8/9 16.4. Flash Write and Erase Guidelines Any system which contains routines which write or erase Flash memory from software involves some risk that the write or erase routines will execute unintentionally if the CPU is operating outside its specified operating range of VDD, system clock frequency, or temperature. This accidental execution of Flash modifying code can result in alteration of Flash memory contents causing a system failure that is only recoverable by re-Flashing the code in the device. The following guidelines are recommended for any system which contains routines which write or erase Flash from code. 16.4.1. VDD Maintenance and the VDD monitor 1. If the system power supply is subject to voltage or current "spikes," add sufficient transient protection devices to the power supply to ensure that the supply voltages listed in the Absolute Maximum Ratings table are not exceeded. 2. Make certain that the minimum VDD rise time specification of 1 ms is met. If the system cannot meet this rise time specification, then add an external VDD brownout circuit to the RST pin of the device that holds the device in reset until VDD reaches 2.7 V and re-asserts RST if VDD drops below 2.7 V. 3. Enable the on-chip VDD monitor and enable the VDD monitor as a reset source as early in code as possible. This should be the first set of instructions executed after the Reset Vector. For 'C'based systems, this will involve modifying the startup code added by the 'C' compiler. See your compiler documentation for more details. Make certain that there are no delays in software between enabling the VDD monitor and enabling the VDD monitor as a reset source. Code examples showing this can be found in "AN201: Writing to Flash from Firmware", available from the Silicon Laboratories web site. 4. As an added precaution, explicitly enable the VDD monitor and enable the VDD monitor as a reset source inside the functions that write and erase Flash memory. The VDD monitor enable instructions should be placed just after the instruction to set PSWE to a '1', but before the Flash write or erase operation instruction. 5. Make certain that all writes to the RSTSRC (Reset Sources) register use direct assignment operators and explicitly DO NOT use the bit-wise operators (such as AND or OR). For example, "RSTSRC = 0x02" is correct. "RSTSRC |= 0x02" is incorrect. 6. Make certain that all writes to the RSTSRC register explicitly set the PORSF bit to a '1'. Areas to check are initialization code which enables other reset sources, such as the Missing Clock Detector or Comparator, for example, and instructions which force a Software Reset. A global search on "RSTSRC" can quickly verify this. 16.4.2. PSWE Maintenance 7. Reduce the number of places in code where the PSWE bit (b0 in PSCTL) is set to a '1'. There should be exactly one routine in code that sets PSWE to a '1' to write Flash bytes and one routine in code that sets PSWE and PSEE both to a '1' to erase Flash pages. 8. Minimize the number of variable accesses while PSWE is set to a '1'. Handle pointer address updates and loop variable maintenance outside the "PSWE = 1;... PSWE = 0;" area. Code examples showing this can be found in AN201, "Writing to Flash from Firmware", available from the Silicon Laboratories web site. 9. Disable interrupts prior to setting PSWE to a '1' and leave them disabled until after PSWE has been reset to '0'. Any interrupts posted during the Flash write or erase operation will be ser- 102 Rev. 0.2 C8051F336/7/8/9 viced in priority order after the Flash operation has been completed and interrupts have been re-enabled by software. 10. Make certain that the Flash write and erase pointer variables are not located in XRAM. See your compiler documentation for instructions regarding how to explicitly locate variables in different memory areas. 11. Add address bounds checking to the routines that write or erase Flash memory to ensure that a routine called with an illegal address does not result in modification of the Flash. 16.4.3. System Clock 12. If operating from an external crystal, be advised that crystal performance is susceptible to electrical interference and is sensitive to layout and to changes in temperature. If the system is operating in an electrically noisy environment, use the internal oscillator or use an external CMOS clock. 13. If operating from the external oscillator, switch to the internal oscillator during Flash write or erase operations. The external oscillator can continue to run, and the CPU can switch back to the external oscillator after the Flash operation has completed. Additional Flash recommendations and example code can be found in AN201, "Writing to Flash from Firmware", available from the Silicon Laboratories web site. Rev. 0.2 103 C8051F336/7/8/9 SFR Definition 16.1. PSCTL: Program Store R/W Control Bit Name Type Reset R 0 R 0 R 0 R 0 R 0 R 0 7 6 5 4 3 2 1 PSEE R/W 0 0 PSWE R/W 0 SFR Address = 0x8F Bit Name 7:2 1 Function UNUSED Unused. Read = 000000b, Write = don't care. PSEE Program Store Erase Enable Setting this bit (in combination with PSWE) allows an entire page of Flash program memory to be erased. If this bit is logic 1 and Flash writes are enabled (PSWE is logic 1), a write to Flash memory using the MOVX instruction will erase the entire page that contains the location addressed by the MOVX instruction. The value of the data byte written does not matter. 0: Flash program memory erasure disabled. 1: Flash program memory erasure enabled. 0 PSWE Program Store Write Enable Setting this bit allows writing a byte of data to the Flash program memory using the MOVX write instruction. The Flash location should be erased before writing data. 0: Writes to Flash program memory disabled. 1: Writes to Flash program memory enabled; the MOVX write instruction targets Flash memory. 104 Rev. 0.2 C8051F336/7/8/9 SFR Definition 16.2. FLKEY: Flash Lock and Key Bit Name Type Reset 0 0 0 0 7 6 5 4 3 2 1 0 FLKEY[7:0] R/W 0 0 0 0 SFR Address = 0xB7 Bit Name 7:0 FLKEY[7:0] Flash Lock and Key Register. Function Write: This register provides a lock and key function for Flash erasures and writes. Flash writes and erases are enabled by writing 0xA5 followed by 0xF1 to the FLKEY register. Flash writes and erases are automatically disabled after the next write or erase is complete. If any writes to FLKEY are performed incorrectly, or if a Flash write or erase operation is attempted while these operations are disabled, the Flash will be permanently locked from writes or erasures until the next device reset. If an application never writes to Flash, it can intentionally lock the Flash by writing a non-0xA5 value to FLKEY from software. Read: When read, bits 1-0 indicate the current Flash lock state. 00: Flash is write/erase locked. 01: The first key code has been written (0xA5). 10: Flash is unlocked (writes/erases allowed). 11: Flash writes/erases disabled until the next reset. Rev. 0.2 105 C8051F336/7/8/9 SFR Definition 16.3. FLSCL: Flash Scale Bit Name Type Reset 7 FOSE R/W 1 6 Reserved R/W 0 5 Reserved R/W 0 4 Reserved R/W 0 3 Reserved R/W 0 2 Reserved R/W 0 1 Reserved R/W 0 0 Reserved R/W 0 SFR Address = 0xB6 Bit Name 7 FOSE Flash One-shot Enable Function This bit enables the Flash read one-shot (recommended). If the Flash one-shot is disabled, the Flash sense amps are enabled for a full clock cycle during Flash reads, increasing the device power consumption. 0: Flash one-shot disabled. 1: Flash one-shot enabled. 6:0 Reserved Reserved. Must Write 0000000b. 106 Rev. 0.2 C8051F336/7/8/9 17. Power Management Modes The C8051F336/7/8/9 devices have three software programmable power management modes: Idle, Stop, and Suspend. Idle mode and Stop mode are part of the standard 8051 architecture, while Suspend mode is an enhanced power-saving mode implemented by the high-speed oscillator peripheral. Idle mode halts the CPU while leaving the peripherals and clocks active. In Stop mode, the CPU is halted, all interrupts and timers (except the Missing Clock Detector) are inactive, and the internal oscillator is stopped (analog peripherals remain in their selected states; the external oscillator is not affected). Suspend mode is similar to Stop mode in that the internal oscillator and CPU are halted, but the device can wake on events such as a Port Mismatch, Comparator low output, or a Timer 3 overflow. Since clocks are running in Idle mode, power consumption is dependent upon the system clock frequency and the number of peripherals left in active mode before entering Idle. Stop mode and Suspend mode consume the least power because the majority of the device is shut down with no clocks active. SFR Definition 17.1 describes the Power Control Register (PCON) used to control the C8051F336/7/8/9's Stop and Idle power management modes. Suspend mode is controlled by the SUSPEND bit in the OSCICN register (SFR Definition 19.3). Although the C8051F336/7/8/9 has Idle, Stop, and Suspend modes available, more control over the device power can be achieved by enabling/disabling individual peripherals as needed. Each analog peripheral can be disabled when not in use and placed in low power mode. Digital peripherals, such as timers or serial buses, draw little power when they are not in use. Turning off oscillators lowers power consumption considerably, at the expense of reduced functionality. 17.1. Idle Mode Setting the Idle Mode Select bit (PCON.0) causes the hardware to halt the CPU and enter Idle mode as soon as the instruction that sets the bit completes execution. All internal registers and memory maintain their original data. All analog and digital peripherals can remain active during Idle mode. Idle mode is terminated when an enabled interrupt is asserted or a reset occurs. The assertion of an enabled interrupt will cause the Idle Mode Selection bit (PCON.0) to be cleared and the CPU to resume operation. The pending interrupt will be serviced and the next instruction to be executed after the return from interrupt (RETI) will be the instruction immediately following the one that set the Idle Mode Select bit. If Idle mode is terminated by an internal or external reset, the CIP-51 performs a normal reset sequence and begins program execution at address 0x0000. Note: If the instruction following the write of the IDLE bit is a single-byte instruction and an interrupt occurs during the execution phase of the instruction that sets the IDLE bit, the CPU may not wake from Idle mode when a future interrupt occurs. Therefore, instructions that set the IDLE bit should be followed by an instruction that has two or more opcode bytes, for example: // in `C': PCON |= 0x01; PCON = PCON; ; in assembly: ORL PCON, #01h MOV PCON, PCON // set IDLE bit // ... followed by a 3-cycle dummy instruction ; set IDLE bit ; ... followed by a 3-cycle dummy instruction If enabled, the Watchdog Timer (WDT) will eventually cause an internal watchdog reset and thereby terminate the Idle mode. This feature protects the system from an unintended permanent shutdown in the event of an inadvertent write to the PCON register. If this behavior is not desired, the WDT may be disabled by Rev. 0.2 107 C8051F336/7/8/9 software prior to entering the Idle mode if the WDT was initially configured to allow this operation. This provides the opportunity for additional power savings, allowing the system to remain in the Idle mode indefinitely, waiting for an external stimulus to wake up the system. Refer to Section "18.6. PCA Watchdog Timer Reset" on page 114 for more information on the use and configuration of the WDT. 17.2. Stop Mode Setting the Stop Mode Select bit (PCON.1) causes the controller core to enter Stop mode as soon as the instruction that sets the bit completes execution. In Stop mode the internal oscillator, CPU, and all digital peripherals are stopped; the state of the external oscillator circuit is not affected. Each analog peripheral (including the external oscillator circuit) may be shut down individually prior to entering Stop Mode. Stop mode can only be terminated by an internal or external reset. On reset, the device performs the normal reset sequence and begins program execution at address 0x0000. If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the Stop mode. The Missing Clock Detector should be disabled if the CPU is to be put to in STOP mode for longer than the MCD timeout of 100 s. 17.3. Suspend Mode Setting the SUSPEND bit (OSCICN.5) causes the hardware to halt the CPU and the high-frequency internal oscillator, and go into Suspend mode as soon as the instruction that sets the bit completes execution. All internal registers and memory maintain their original data. Most digital peripherals are not active in Suspend mode. The exception to this is the Port Match feature and Timer 3, when it is run from an external oscillator source or the internal low-frequency oscillator. Suspend mode can be terminated by four types of events, a port match (described in Section "20.5. Port Match" on page 136), a Timer 3 overflow (described in Section "24.3. Timer 3" on page 203), a Comparator low output (if enabled), or a device reset event. Note that in order to run Timer 3 in Suspend mode, the timer must be configured to clock from either the external clock source or the internal low-frequency oscillator source. When Suspend mode is terminated, the device will continue execution on the instruction following the one that set the SUSPEND bit. If the wake event (port match or Timer 3 overflow) was configured to generate an interrupt, the interrupt will be serviced upon waking the device. If Suspend mode is terminated by an internal or external reset, the CIP-51 performs a normal reset sequence and begins program execution at address 0x0000. 108 Rev. 0.2 C8051F336/7/8/9 SFR Definition 17.1. PCON: Power Control Bit Name Type Reset 0 0 0 7 6 5 GF[5:0] R/W 0 0 0 4 3 2 1 STOP R/W 0 0 IDLE R/W 0 SFR Address = 0x87 Bit Name 7:2 1 GF[5:0] STOP General Purpose Flags 5-0. Function These are general purpose flags for use under software control. Stop Mode Select. Setting this bit will place the CIP-51 in Stop mode. This bit will always be read as 0. 1: CPU goes into Stop mode (internal oscillator stopped). IDLE: Idle Mode Select. Setting this bit will place the CIP-51 in Idle mode. This bit will always be read as 0. 1: CPU goes into Idle mode. (Shuts off clock to CPU, but clock to Timers, Interrupts, Serial Ports, and Analog Peripherals are still active.) 0 IDLE Rev. 0.2 109 C8051F336/7/8/9 18. Reset Sources Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur: * CIP-51 halts program execution * Special Function Registers (SFRs) are initialized to their defined reset values * External Port pins are forced to a known state * Interrupts and timers are disabled. All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal data memory are unaffected during a reset; any previously stored data is preserved. However, since the stack pointer SFR is reset, the stack is effectively lost, even though the data on the stack is not altered. The Port I/O latches are reset to 0xFF (all logic ones) in open-drain mode. Weak pullups are enabled during and after the reset. For VDD Monitor and power-on resets, the RST pin is driven low until the device exits the reset state. On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the internal oscillator. The Watchdog Timer is enabled with the system clock divided by 12 as its clock source. Program execution begins at location 0x0000. VDD Power On Reset Supply Monitor Px.x Px.x Comparator 0 + C0RSEF + - Enable '0' (wired-OR) /RST Missing Clock Detector (oneshot) EN Reset Funnel PCA WDT (Software Reset) SWRSF EN MCD Enable System Clock CIP-51 Microcontroller Core Extended Interrupt Handler WDT Enable Errant FLASH Operation System Reset Figure 18.1. Reset Sources 110 Rev. 0.2 C8051F336/7/8/9 18.1. Power-On Reset During power-up, the device is held in a reset state and the RST pin is driven low until VDD settles above VRST. A delay occurs before the device is released from reset; the delay decreases as the VDD ramp time increases (VDD ramp time is defined as how fast VDD ramps from 0 V to VRST). Figure 18.2. plots the power-on and VDD monitor reset timing. The maximum VDD ramp time is 1 ms; slower ramp times may cause the device to be released from reset before VDD reaches the VRST level. For ramp times less than 1 ms, the power-on reset delay (TPORDelay) is typically less than 0.3 ms. On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other resets). Since all resets cause program execution to begin at the same location (0x0000) software can read the PORSF flag to determine if a power-up was the cause of reset. The content of internal data memory should be assumed to be undefined after a power-on reset. The VDD monitor is enabled following a power-on reset. volts VDD VRST 2.70 2.55 2.0 1.0 VD D t Logic HIGH /RST Logic LOW TPORDelay VDD Monitor Reset Power-On Reset Figure 18.2. Power-On and VDD Monitor Reset Timing Rev. 0.2 111 C8051F336/7/8/9 18.2. Power-Fail Reset / VDD Monitor When a power-down transition or power irregularity causes VDD to drop below VRST, the power supply monitor will drive the RST pin low and hold the CIP-51 in a reset state (see Figure 18.2). When VDD returns to a level above VRST, the CIP-51 will be released from the reset state. Note that even though internal data memory contents are not altered by the power-fail reset, it is impossible to determine if VDD dropped below the level required for data retention. If the PORSF flag reads `1', the data may no longer be valid. The VDD monitor is enabled after power-on resets. Its defined state (enabled/disabled) is not altered by any other reset source. For example, if the VDD monitor is disabled by code and a software reset is performed, the VDD monitor will still be disabled after the reset. Important Note: If the VDD monitor is being turned on from a disabled state, it should be enabled before it is selected as a reset source. Selecting the VDD monitor as a reset source before it is enabled and stabilized may cause a system reset. In some applications, this reset may be undesirable. If this is not desirable in the application, a delay should be introduced between enabling the monitor and selecting it as a reset source. The procedure for enabling the VDD monitor and configuring it as a reset source from a disabled state is shown below: Step 1. Enable the VDD monitor (VDMEN bit in VDM0CN = `1'). Step 2. If necessary, wait for the VDD monitor to stabilize (see Table 6.4 for the VDD Monitor turnon time). Step 3. Select the VDD monitor as a reset source (PORSF bit in RSTSRC = `1'). See Figure 18.2 for VDD monitor timing; note that the power-on-reset delay is not incurred after a VDD monitor reset. See Table 6.4 for complete electrical characteristics of the VDD monitor. 112 Rev. 0.2 C8051F336/7/8/9 SFR Definition 18.1. VDM0CN: VDD Monitor Control Bit Name Type Reset 7 VDMEN R/W Varies 6 VDDSTAT R Varies R 0 R 0 R 0 R 0 R 0 R 0 5 4 3 2 1 0 SFR Address = 0xFF Bit Name 7 VDMEN VDD Monitor Enable. Function This bit turns the VDD monitor circuit on/off. The VDD Monitor cannot generate system resets until it is also selected as a reset source in register RSTSRC (SFR Definition 18.2). Selecting the VDD monitor as a reset source before it has stabilized may generate a system reset. In systems where this reset would be undesirable, a delay should be introduced between enabling the VDD Monitor and selecting it as a reset source. See Table 6.4 for the minimum VDD Monitor turn-on time. 0: VDD Monitor Disabled. 1: VDD Monitor Enabled. 6 VDDSTAT VDD Status. This bit indicates the current power supply status (VDD Monitor output). 0: VDD is at or below the VDD monitor threshold. 1: VDD is above the VDD monitor threshold. 5:0 UNUSED Unused. Read = 000000b; Write = Don't care. 18.3. External Reset The external RST pin provides a means for external circuitry to force the device into a reset state. Asserting an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the RST pin may be necessary to avoid erroneous noise-induced resets. See Table 6.4 for complete RST pin specifications. The PINRSF flag (RSTSRC.0) is set on exit from an external reset. 18.4. Missing Clock Detector Reset The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If the system clock remains high or low for more than 100 s, the one-shot will time out and generate a reset. After a MCD reset, the MCDRSF flag (RSTSRC.2) will read `1', signifying the MCD as the reset source; otherwise, this bit reads `0'. Writing a `1' to the MCDRSF bit enables the Missing Clock Detector; writing a `0' disables it. The state of the RST pin is unaffected by this reset. Rev. 0.2 113 C8051F336/7/8/9 18.5. Comparator0 Reset Comparator0 can be configured as a reset source by writing a `1' to the C0RSEF flag (RSTSRC.5). Comparator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on chatter on the output from generating an unwanted reset. The Comparator0 reset is active-low: if the noninverting input voltage (on CP0+) is less than the inverting input voltage (on CP0-), the device is put into the reset state. After a Comparator0 reset, the C0RSEF flag (RSTSRC.5) will read `1' signifying Comparator0 as the reset source; otherwise, this bit reads `0'. The state of the RST pin is unaffected by this reset. 18.6. PCA Watchdog Timer Reset The programmable Watchdog Timer (WDT) function of the Programmable Counter Array (PCA) can be used to prevent software from running out of control during a system malfunction. The PCA WDT function can be enabled or disabled by software as described in Section "25.4. Watchdog Timer Mode" on page 221; the WDT is enabled and clocked by SYSCLK / 12 following any reset. If a system malfunction prevents user software from updating the WDT, a reset is generated and the WDTRSF bit (RSTSRC.5) is set to `1'. The state of the RST pin is unaffected by this reset. 18.7. Flash Error Reset If a Flash read/write/erase or program read targets an illegal address, a system reset is generated. This may occur due to any of the following: A Flash write or erase is attempted above user code space. This occurs when PSWE is set to `1' and a MOVX write operation targets an address above address 0x3DFF. * A Flash read is attempted above user code space. This occurs when a MOVC operation targets an address above address 0x3DFF. * A Program read is attempted above user code space. This occurs when user code attempts to branch to an address above 0x3DFF. * A Flash read, write or erase attempt is restricted due to a Flash security setting (see Section "16.3. Security Options" on page 100). The FERROR bit (RSTSRC.6) is set following a Flash error reset. The state of the RST pin is unaffected by this reset. * 18.8. Software Reset Software may force a reset by writing a `1' to the SWRSF bit (RSTSRC.4). The SWRSF bit will read `1' following a software forced reset. The state of the RST pin is unaffected by this reset. 114 Rev. 0.2 C8051F336/7/8/9 SFR Definition 18.2. RSTSRC: Reset Source Bit Name Type Reset R 0 7 6 FERROR R Varies 5 C0RSEF R/W Varies 4 SWRSF R/W Varies 3 WDTRSF R Varies 2 MCDRSF R/W Varies 1 PORSF R/W Varies 0 PINRSF R Varies SFR Address = 0xEF Bit Name 7 6 UNUSED Unused. Description Write Don't care. N/A 0 Read FERROR Flash Error Reset Flag. Set to `1' if Flash read/write/erase error caused the last reset. Set to `1' if Comparator0 caused the last reset. Set to `1' if last reset was caused by a write to SWRSF. Set to `1' if Watchdog Timer overflow caused the last reset. 5 C0RSEF Comparator0 Reset Enable and Flag. SWRSF Software Reset Force and Flag. Writing a `1' enables Comparator0 as a reset source (active-low). Writing a `1' forces a system reset. 4 3 WDTRSF Watchdog Timer Reset Flag. N/A 2 MCDRSF Missing Clock Detector Enable and Flag. Writing a `1' enables the Set to `1' if Missing Clock Missing Clock Detector. Detector timeout caused The MCD triggers a reset the last reset. if a missing clock condition is detected. Set to `1' anytime a poweron or VDD monitor reset occurs. When set to `1' all other RSTSRC flags are indeterminate. 1 PORSF Power-On / VDD Monitor Writing a `1' enables the Reset Flag, and VDD monitor VDD monitor as a reset source. Reset Enable. Writing `1' to this bit before the VDD monitor is enabled and stabilized may cause a system reset. HW Pin Reset Flag. N/A 0 PINRSF Set to `1' if RST pin caused the last reset. Note: Do not use read-modify-write operations on this register Rev. 0.2 115 C8051F336/7/8/9 19. Oscillators and Clock Selection C8051F336/7/8/9 devices include a programmable internal high-frequency oscillator, a programmable internal low-frequency oscillator, and an external oscillator drive circuit. The internal high-frequency oscillator can be enabled/disabled and calibrated using the OSCICN and OSCICL registers, as shown in Figure 19.1. The internal low-frequency oscillator can be enabled/disabled and calibrated using the OSCLCN register. The system clock can be sourced by the external oscillator circuit or either internal oscillator. Both internal oscillators offer a selectable post-scaling feature. OSCICL IOSCEN IFRDY OSCICN IFCN1 IFCN0 OSCLCN OSCLEN OSCLRDY OSCLF3 OSCLF2 OSCLF1 OSCLF0 OSCLD1 OSCLD0 OSCLF OSCLD SYSCLK n Option 3 XTAL2 Programmable Internal Clock Generator OSCLF EN EN n Option 4 XTAL2 Option 2 VDD Option 1 XTAL1 XTAL2 10M XTAL2 Low Frequency Oscillator OSCLD Input Circuit OSC XTLVLD XOSCMD2 XOSCMD1 XOSCMD0 XFCN2 XFCN1 XFCN0 OSCXCN CLKSEL Figure 19.1. Oscillator Options 116 Rev. 0.2 SEL1 SEL0 C8051F336/7/8/9 19.1. System Clock Selection The CLKSL[1:0] bits in register CLKSEL select which oscillator source is used as the system clock. CLKSL[1:0] must be set to 01b for the system clock to run from the external oscillator; however the external oscillator may still clock certain peripherals (timers, PCA) when the internal oscillator is selected as the system clock. The system clock may be switched on-the-fly between the internal oscillator, external oscillator, and Clock Multiplier so long as the selected clock source is enabled and has settled. The internal high-frequency and low-frequency oscillators require little start-up time and may be selected as the system clock immediately following the register write which enables the oscillator. The external RC and C modes also typically require no startup time. External crystals and ceramic resonators however, typically require a start-up time before they are settled and ready for use. The Crystal Valid Flag (XTLVLD in register OSCXCN) is set to '1' by hardware when the external crystal or ceramic resonator is settled. In crystal mode, to avoid reading a false XTLVLD, software should delay at least 1 ms between enabling the external oscillator and checking XTLVLD. SFR Definition 19.1. CLKSEL: Clock Select Bit Name Type Reset R 0 R 0 R 0 R 0 R 0 R 0 0 7 6 5 4 3 2 1 0 CLKSL[1:0] R/W 0 SFR Address = 0xA9; Bit Name 7:2 1:0 UNUSED Function Unused. Read = 000000b; Write = Don't Care 00: SYSCLK derived from the Internal High-Frequency Oscillator and scaled per the IFCN bits in register OSCICN. 01: SYSCLK derived from the External Oscillator circuit. 10: SYSCLK derived from the Internal Low-Frequency Oscillator and scaled per the OSCLD bits in register OSCLCN. 11: reserved. CLKSL[1:0] System Clock Source Select Bits. Rev. 0.2 117 C8051F336/7/8/9 19.2. Programmable Internal High-Frequency (H-F) Oscillator All C8051F336/7/8/9 devices include a programmable internal high-frequency oscillator that defaults as the system clock after a system reset. The internal oscillator period can be adjusted via the OSCICL register as defined by SFR Definition 19.2. On C8051F336/7/8/9 devices, OSCICL is factory calibrated to obtain a 24.5 MHz base frequency. Note that the system clock may be derived from the programmed internal oscillator divided by 1, 2, 4, or 8, as defined by the IFCN bits in register OSCICN. The divide value defaults to 8 following a reset. 19.2.1. Internal Oscillator Suspend Mode When software writes a logic 1 to SUSPEND (OSCICN.5), the internal oscillator is suspended. If the system clock is derived from the internal oscillator, the input clock to the peripheral or CIP-51 will be stopped until one of the following events occur: * * * * Port 0 Match Event. Port 1 Match Event. Comparator 0 enabled and output is logic 0. Timer3 Overflow Event. When one of the oscillator awakening events occur, the internal oscillator, CIP-51, and affected peripherals resume normal operation, regardless of whether the event also causes an interrupt. The CPU resumes execution at the instruction following the write to SUSPEND. SFR Definition 19.2. OSCICL: Internal H-F Oscillator Calibration Bit Name Type Reset R 0 Varies Varies Varies 7 6 5 4 3 OSCICL[6:0] R/W Varies Varies Varies Varies 2 1 0 SFR Address = 0xB3; Bit Name 7 6:0 UNUSED Function Unused. Read = 0; Write = Don't Care These bits determine the internal oscillator period. When set to 0000000b, the H-F oscillator operates at its fastest setting. When set to 1111111b, the H-F oscillator operates at its slowest setting. The reset value is factory calibrated to generate an internal oscillator frequency of 24.5 MHz. OSCICL[6:0] Internal Oscillator Calibration Bits. 118 Rev. 0.2 C8051F336/7/8/9 SFR Definition 19.3. OSCICN: Internal H-F Oscillator Control Bit Name Type Reset 7 IOSCEN R/W 1 6 IFRDY R 1 5 SUSPEND R/W 0 4 STSYNC R 0 R 0 R 0 0 3 2 1 IFCN[1:0] R/W 0 0 SFR Address = 0xB2; Bit Name 7 IOSCEN Internal H-F Oscillator Enable Bit. 0: Internal H-F Oscillator Disabled. 1: Internal H-F Oscillator Enabled. 6 IFRDY Function Internal H-F Oscillator Frequency Ready Flag. 0: Internal H-F Oscillator is not running at programmed frequency. 1: Internal H-F Oscillator is running at programmed frequency. 5 SUSPEND Internal Oscillator Suspend Enable Bit. Setting this bit to logic 1 places the internal oscillator in SUSPEND mode. The internal oscillator resumes operation when one of the SUSPEND mode awakening events occurs. 4 STSYNC Suspend Timer Synchronization Bit. This bit is used to indicate when it is safe to read and write the registers associated with the suspend wake-up timer (See Section 17.3 for suspend wake-up details). If a suspend wake-up source other than the timer has brought the oscillator out of suspend mode, it may take up to three timer clocks before the timer can be read or written. When STSYNC reads '1', reads and writes of the timer register should not be performed. When STSYNC reads '0', it is safe to read and write the timer registers. 3:2 1:0 UNUSED IFCN[1:0] Unused. Read = 00b; Write = Don't Care Internal H-F Oscillator Frequency Divider Control Bits. 00: SYSCLK derived from Internal H-F Oscillator divided by 8. 01: SYSCLK derived from Internal H-F Oscillator divided by 4. 10: SYSCLK derived from Internal H-F Oscillator divided by 2. 11: SYSCLK derived from Internal H-F Oscillator divided by 1. Rev. 0.2 119 C8051F336/7/8/9 19.3. Programmable Internal Low-Frequency (L-F) Oscillator All C8051F336/7/8/9 devices include a programmable low-frequency internal oscillator, which is calibrated to a nominal frequency of 80 kHz. The low-frequency oscillator circuit includes a divider that can be changed to divide the clock by 1, 2, 4, or 8, using the OSCLD bits in the OSCLCN register (see SFR Definition 19.4). Additionally, the OSCLF[3:0] bits can be used to adjust the oscillator's output frequency. 19.3.1. Calibrating the Internal L-F Oscillator Timers 2 and 3 include capture functions that can be used to capture the oscillator frequency, when running from a known time base. When either Timer 2 or Timer 3 is configured for L-F Oscillator Capture Mode, a falling edge (Timer 2) or rising edge (Timer 3) of the low-frequency oscillator's output will cause a capture event on the corresponding timer. As a capture event occurs, the current timer value (TMRnH:TMRnL) is copied into the timer reload registers (TMRnRLH:TMRnRLL). By recording the difference between two successive timer capture values, the low-frequency oscillator's period can be calculated. The OSCLF bits can then be adjusted to produce the desired oscillator frequency. SFR Definition 19.4. OSCLCN: Internal L-F Oscillator Control Bit Name Type Reset 7 OSCLEN R/W 0 6 OSCLRDY R 0 Varies Varies 5 4 3 2 1 0 OSCLF[3:0] R.W Varies Varies OSCLD[1:0] R/W 0 0 SFR Address = 0xE3; Bit Name 7 OSCLEN Internal L-F Oscillator Enable. 0: Internal L-F Oscillator Disabled. 1: Internal L-F Oscillator Enabled. 6 OSCLRDY Internal L-F Oscillator Ready. Function 0: Internal L-F Oscillator frequency not stabilized. 1: Internal L-F Oscillator frequency stabilized. 5:2 OSCLF[3:0] Internal L-F Oscillator Frequency Control bits. Fine-tune control bits for the Internal L-F oscillator frequency. When set to 0000b, the L-F oscillator operates at its fastest setting. When set to 1111b, the L-F oscillator operates at its slowest setting. 1:0 OSCLD[1:0] Internal L-F Oscillator Divider Select. 00: Divide by 8 selected. 01: Divide by 4 selected. 10: Divide by 2 selected. 11: Divide by 1 selected. 120 Rev. 0.2 C8051F336/7/8/9 19.4. External Oscillator Drive Circuit The external oscillator circuit may drive an external crystal, ceramic resonator, capacitor, or RC network. A CMOS clock may also provide a clock input. For a crystal or ceramic resonator configuration, the crystal/resonator must be wired across the XTAL1 and XTAL2 pins as shown in Option 1 of Figure 19.1. A 10 M resistor also must be wired across the XTAL2 and XTAL1 pins for the crystal/resonator configuration. In RC, capacitor, or CMOS clock configuration, the clock source should be wired to the XTAL2 pin as shown in Option 2, 3, or 4 of Figure 19.1. The type of external oscillator must be selected in the OSCXCN register, and the frequency control bits (XFCN) must be selected appropriately (see SFR Definition 19.5). Important Note on External Oscillator Usage: Port pins must be configured when using the external oscillator circuit. When the external oscillator drive circuit is enabled in crystal/resonator mode, Port pins P0.2 and P0.3 are used as XTAL1 and XTAL2 respectively. When the external oscillator drive circuit is enabled in capacitor, RC, or CMOS clock mode, Port pin P0.3 is used as XTAL2. The Port I/O Crossbar should be configured to skip the Port pins used by the oscillator circuit; see Section "20.3. Priority Crossbar Decoder" on page 131 for Crossbar configuration. Additionally, when using the external oscillator circuit in crystal/resonator, capacitor, or RC mode, the associated Port pins should be configured as analog inputs. In CMOS clock mode, the associated pin should be configured as a digital input. See Section "20.4. Port I/O Initialization" on page 133 for details on Port input mode selection. Rev. 0.2 121 C8051F336/7/8/9 SFR Definition 19.5. OSCXCN: External Oscillator Control Bit Name Type Reset 7 XTLVLD R 0 0 6 5 XOSCMD[2:0] R/W 0 0 R 0 0 4 3 2 1 XFCN[2:0] R/W 0 0 0 SFR Address = 0xB1; Bit Name 7 XTLVLD Crystal Oscillator Valid Flag. Function (Read only when XOSCMD = 11x.) 0: Crystal Oscillator is unused or not yet stable. 1: Crystal Oscillator is running and stable. 6:4 XOSCMD[2:0] External Oscillator Mode Select. 00x: External Oscillator circuit off. 010: External CMOS Clock Mode. 011: External CMOS Clock Mode with divide by 2 stage. 100: RC Oscillator Mode. 101: Capacitor Oscillator Mode. 110: Crystal Oscillator Mode. 111: Crystal Oscillator Mode with divide by 2 stage. 3 2:0 UNUSED XFCN[2:0] Read = 0; Write = Don't Care External Oscillator Frequency Control Bits. Set according to the desired frequency for Crystal or RC mode. Set according to the desired K Factor for C mode. XFCN 000 001 010 011 100 101 110 111 Crystal Mode f 32 kHz 32 kHz < f 84 kHz 84 kHz < f 225 kHz 225 kHz < f 590 kHz 590 kHz < f 1.5 MHz 1.5 MHz < f 4 MHz 4 MHz < f 10 MHz 10 MHz < f 30 MHz RC Mode f 25 kHz 25 kHz < f 50 kHz 50 kHz < f 100 kHz 100 kHz < f 200 kHz 200 kHz < f 400 kHz 400 kHz < f 800 kHz 800 kHz < f 1.6 MHz 1.6 MHz < f 3.2 MHz C Mode K Factor = 0.87 K Factor = 2.6 K Factor = 7.7 K Factor = 22 K Factor = 65 K Factor = 180 K Factor = 664 K Factor = 1590 122 Rev. 0.2 C8051F336/7/8/9 19.4.1. External Crystal Example If a crystal or ceramic resonator is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 19.1, Option 1. The External Oscillator Frequency Control value (XFCN) should be chosen from the Crystal column of the table in SFR Definition 19.5 (OSCXCN register). For example, an 11.0592 MHz crystal requires an XFCN setting of 111b and a 32.768 kHz Watch Crystal requires an XFCN setting of 001b. After an external 32.768 kHz oscillator is stabilized, the XFCN setting can be switched to 000 to save power. It is recommended to enable the missing clock detector before switching the system clock to any external oscillator source. When the crystal oscillator is first enabled, the oscillator amplitude detection circuit requires a settling time to achieve proper bias. Introducing a delay of 1 ms between enabling the oscillator and checking the XTLVLD bit will prevent a premature switch to the external oscillator as the system clock. Switching to the external oscillator before the crystal oscillator has stabilized can result in unpredictable behavior. The recommended procedure is: Step 1. Force XTAL1 and XTAL2 to a low state. This involves enabling the Crossbar and writing `0' to the port pins associated with XTAL1 and XTAL2. Step 2. Configure XTAL1 and XTAL2 as analog inputs using. Step 3. Enable the external oscillator. Step 4. Wait at least 1 ms. Step 5. Poll for XTLVLD => `1'. Step 6. Enable the Missing Clock Detector. Step 7. Switch the system clock to the external oscillator. Important Note on External Crystals: Crystal oscillator circuits are quite sensitive to PCB layout. The crystal should be placed as close as possible to the XTAL pins on the device. The traces should be as short as possible and shielded with ground plane from any other traces which could introduce noise or interference. Rev. 0.2 123 C8051F336/7/8/9 The capacitors shown in the external crystal configuration provide the load capacitance required by the crystal for correct oscillation. These capacitors are "in series" as seen by the crystal and "in parallel" with the stray capacitance of the XTAL1 and XTAL2 pins. Note: The desired load capacitance depends upon the crystal and the manufacturer. Please refer to the crystal data sheet when completing these calculations. For example, a tuning-fork crystal of 32.768 kHz with a recommended load capacitance of 12.5 pF should use the configuration shown in Figure 19.1, Option 1. The total value of the capacitors and the stray capacitance of the XTAL pins should equal 25 pF. With a stray capacitance of 3 pF per pin, the 22 pF capacitors yield an equivalent capacitance of 12.5 pF across the crystal, as shown in Figure 19.2. XTAL1 10M XTAL2 32.768 kHz 22pF* 22pF* * Capacitor values depend on crystal specifications Figure 19.2. External 32.768 kHz Quartz Crystal Oscillator Connection Diagram 124 Rev. 0.2 C8051F336/7/8/9 19.4.2. External RC Example If an RC network is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 19.1, Option 2. The capacitor should be no greater than 100 pF; however for very small capacitors, the total capacitance may be dominated by parasitic capacitance in the PCB layout. To determine the required External Oscillator Frequency Control value (XFCN) in the OSCXCN Register, first select the RC network value to produce the desired frequency of oscillation, according to Equation 1, where f = the frequency of oscillation in MHz, C = the capacitor value in pF, and R = the pull-up resistor value in k. Equation 1. RC Mode Oscillator Frequency f = 1.23 x 10 ( R x C ) 3 For example: If the frequency desired is 100 kHz, let R = 246 k and C = 50 pF: f = 1.23( 103 ) / RC = 1.23 ( 103 ) / [ 246 x 50 ] = 0.1 MHz = 100 kHz Referring to the table in SFR Definition 19.5, the required XFCN setting is 010b. 19.4.3. External Capacitor Example If a capacitor is used as an external oscillator for the MCU, the circuit should be configured as shown in Figure 19.1, Option 3. The capacitor should be no greater than 100 pF; however for very small capacitors, the total capacitance may be dominated by parasitic capacitance in the PCB layout. To determine the required External Oscillator Frequency Control value (XFCN) in the OSCXCN Register, select the capacitor to be used and find the frequency of oscillation according to Equation 2, where f = the frequency of oscillation in MHz, C = the capacitor value in pF, and VDD = the MCU power supply in Volts. Equation 2. C Mode Oscillator Frequency f = ( KF ) ( R x V DD ) For example: Assume VDD = 3.0 V and f = 150 kHz: f = KF / (C x VDD) 0.150 MHz = KF / (C x 3.0) Since the frequency of roughly 150 kHz is desired, select the K Factor from the table in SFR Definition 19.5 (OSCXCN) as KF = 22: 0.150 MHz = 22 / (C x 3.0) C x 3.0 = 22 / 0.150 MHz C = 146.6 / 3.0 pF = 48.8 pF Therefore, the XFCN value to use in this example is 011b and C = 50 pF. Rev. 0.2 125 C8051F336/7/8/9 20. Port Input/Output Digital and analog resources are available through 17 (C8051F336/7) or 21 (C8051F338/9) I/O pins. Port pins P0.0-P2.3 can be defined as general-purpose I/O (GPIO), assigned to one of the internal digital resources, or assigned to an analog function as shown in Figure 20.3. Port pin P2.4 on the C8051F338/9 and P2.0 on the C8051F336/7 can be used as GPIO and are shared with the C2 Interface Data signal (C2D). The designer has complete control over which functions are assigned, limited only by the number of physical I/O pins. This resource assignment flexibility is achieved through the use of a Priority Crossbar Decoder. Note that the state of a Port I/O pin can always be read in the corresponding Port latch, regardless of the Crossbar settings. The Crossbar assigns the selected internal digital resources to the I/O pins based on the Priority Decoder (Figure 20.3 and Figure 20.4). The registers XBR0 and XBR1, defined in SFR Definition 20.1 and SFR Definition 20.2, are used to select internal digital functions. All Port I/Os are 5 V tolerant (refer to Figure 20.2 for the Port cell circuit). The Port I/O cells are configured as either push-pull or open-drain in the Port Output Mode registers (PnMDOUT, where n = 0,1). Complete Electrical Specifications for Port I/O are given in Table 6.3 on page 36. 126 Rev. 0.2 C8051F336/7/8/9 Port Match P0MASK, P0MAT P1MASK, P1MAT XBR0, XBR1, PnSKIP Registers Priority Decoder UART SPI (Internal Digital Signals) SMBus 2 2 4 2 External Interrupts EX0 and EX1 PnMDOUT, PnMDIN Registers Highest Priority P0.0 Digital Crossbar 8 P0 I/O Cells P0.7 P1.0 P1 I/O Cells P1.7 CP0 Outputs SYSCLK PCA 8 4 2 8 Lowest Priority T0, T1 P0 (Port Latches) 4 (P0.0-P0.7) 8 P2 I/O Cell P2.0 P2.3* P1 (P1.0-P1.7) 4 P2 (P2.0-P2.3*) To Analog Peripherals (ADC0, CP0, VREF, XTAL) *P2.1-P2.3 only available on QFN24 Packages Figure 20.1. Port I/O Functional Block Diagram 20.1. Port I/O Modes of Operation Port pins P0.0 - P2.3 use the Port I/O cell shown in Figure 20.2. Each Port I/O cell can be configured by software for analog I/O or digital I/O using the PnMDIN registers. On reset, all Port I/O cells default to a high impedance state with weak pull-ups enabled until the Crossbar is enabled (XBARE = `1'). 20.1.1. Port Pins Configured for Analog I/O Any pins to be used as Comparator or ADC input, external oscillator input/output, VREF, or IDAC output should be configured for analog I/O (PnMDIN.n = `1'). When a pin is configured for analog I/O, its weak pullup, digital driver, and digital receiver are disabled. Port pins configured for analog I/O will always read back a value of `0'. Configuring pins as analog I/O saves power and isolates the Port pin from digital interference. Port pins configured as digital inputs may still be used by analog peripherals; however, this practice is not recommended and may result in measurement errors. Rev. 0.2 127 C8051F336/7/8/9 20.1.2. Port Pins Configured For Digital I/O Any pins to be used by digital peripherals (UART, SPI, SMBus, etc.), external digital event capture functions, or as GPIO should be configured as digital I/O (PnMDIN.n = `1'). For digital I/O pins, one of two output modes (push-pull or open-drain) must be selected using the PnMDOUT registers. Push-pull outputs (PnMDOUT.n = `1') drive the Port pad to the VDD/DC+ or GND supply rails based on the output logic value of the Port pin. Open-drain outputs have the high side driver disabled; therefore, they only drive the Port pad to GND when the output logic value is `0' and become high impedance inputs (both high low drivers turned off) when the output logic value is `1'. When a digital I/O cell is placed in the high impedance state, a weak pull-up transistor pulls the Port pad to the VDD supply voltage to ensure the digital input is at a defined logic state. Weak pull-ups are disabled when the I/O cell is driven to GND to minimize power consumption and may be globally disabled by setting WEAKPUD to `1'. The user should ensure that digital I/O are always internally or externally pulled or driven to a valid logic state to minimize power consumption. Port pins configured for digital I/O always read back the logic state of the Port pad, regardless of the output logic value of the Port pin. WEAKPUD (Weak Pull-Up Disable) PxMDOUT.x (1 for push-pull) (0 for open-drain) XBARE (Crossbar Enable) Px.x - Output Logic Value (Port Latch or Crossbar) PxMDIN.x (1 for digital) (0 for analog) To/From Analog Peripheral Px.x - Input Logic Value (Reads 0 when pin is configured as an analog I/O) GND VDD VDD (WEAK) PORT PAD Figure 20.2. Port I/O Cell Block Diagram 20.1.3. Interfacing Port I/O to 5V Logic All Port I/O configured for digital, open-drain operation are capable of interfacing to digital logic operating at a supply voltage higher than VDD and less than 5.25V. An external pull-up resistor to the higher supply voltage is typically required for most systems. Important Note: In a multi-voltage interface, the external pull-up resistor should be sized to allow a current of at least 150uA to flow into the Port pin when the supply voltage is between (VDD + 0.6V) and (VDD + 1.0V). Once the Port pin voltage increases beyond this range, the current flowing into the Port pin is minimal. 128 Rev. 0.2 C8051F336/7/8/9 20.2. Assigning Port I/O Pins to Analog and Digital Functions Port I/O pins P0.0 - P2.3 can be assigned to various analog, digital, and external interrupt functions. The Port pins assigned to analog functions should be configured for analog I/O, and Port pins assigned to digital or external interrupt functions should be configured for digital I/O. 20.2.1. Assigning Port I/O Pins to Analog Functions Table 20.1 shows all available analog functions that require Port I/O assignments. Port pins selected for these analog functions should have their corresponding bit in PnSKIP set to `1'. This reserves the pin for use by the analog function and does not allow it to be claimed by the Crossbar. Table 20.1 shows the potential mapping of Port I/O to each analog function. Table 20.1. Port I/O Assignment for Analog Functions Analog Function ADC Input Comparator0 Input Voltage Reference (VREF0) Current DAC Output (IDA0) External Oscillator in Crystal Mode (XTAL1) External Oscillator in RC, C, or Crystal Mode (XTAL2) Potentially Assignable Port Pins P0.0 - P2.3 P0.0 - P2.3 P0.0 P0.1 P0.2 P0.3 SFR(s) used for Assignment AMX0P, AMX0N, PnSKIP CPT0MX, PnSKIP REF0CN, PnSKIP IDA0CN, PnSKIP OSCXCN, PnSKIP OSCXCN, PnSKIP Rev. 0.2 129 C8051F336/7/8/9 20.2.2. Assigning Port I/O Pins to Digital Functions Any Port pins not assigned to analog functions may be assigned to digital functions or used as GPIO. Most digital functions rely on the Crossbar for pin assignment; however, some digital functions bypass the Crossbar in a manner similar to the analog functions listed above. Port pins used by these digital functions and any Port pins selected for use as GPIO should have their corresponding bit in PnSKIP set to `1'. Table 20.2 shows all available digital functions and the potential mapping of Port I/O to each digital function. Table 20.2. Port I/O Assignment for Digital Functions Digital Function Potentially Assignable Port Pins SFR(s) used for Assignment XBR0, XBR1 UART0, SPI0, SMBus, CP0, Any Port pin available for assignment by the CP0A, SYSCLK, PCA0 Crossbar. This includes P0.0 - P2.3 pins which (CEX0-2 and ECI), T0 or T1. have their PnSKIP bit set to `0'. Note: The Crossbar will always assign UART0 pins to P0.4 and P0.5. Any pin used for GPIO P0.0 - P2.4 P0SKIP, P1SKIP, P2SKIP 20.2.3. Assigning Port I/O Pins to External Digital Event Capture Functions External digital event capture functions can be used to trigger an interrupt or wake the device from a low power mode when a transition occurs on a digital I/O pin. The digital event capture functions do not require dedicated pins and will function on both GPIO pins (PnSKIP = '1') and pins in use by the Crossbar (PnSKIP = `0'). External digital event capture functions cannot be used on pins configured for analog I/O. Table 20.3 shows all available external digital event capture functions. Table 20.3. Port I/O Assignment for External Digital Event Capture Functions Digital Function External Interrupt 0 External Interrupt 1 Port Match Potentially Assignable Port Pins P0.0 - P0.7 P0.0 - P0.7 P0.0 - P1.7 SFR(s) used for Assignment IT01CF IT01CF P0MASK, P0MAT P1MASK, P1MAT 130 Rev. 0.2 C8051F336/7/8/9 20.3. Priority Crossbar Decoder The Priority Crossbar Decoder (Figure 20.3) assigns a priority to each I/O function, starting at the top with UART0. When a digital resource is selected, the least-significant unassigned Port pin is assigned to that resource (excluding UART0, which is always at pins 4 and 5). If a Port pin is assigned, the Crossbar skips that pin when assigning the next selected resource. Additionally, the Crossbar will skip Port pins whose associated bits in the PnSKIP registers are set. The PnSKIP registers allow software to skip Port pins that are to be used for analog input, dedicated functions, or GPIO. Important Note on Crossbar Configuration: If a Port pin is claimed by a peripheral without use of the Crossbar, its corresponding PnSKIP bit should be set. This applies to P0.0 if VREF is used, P0.3 and/or P0.2 if the external oscillator circuit is enabled, P0.6 if the ADC or IDAC is configured to use the external conversion start signal (CNVSTR), and any selected ADC or Comparator inputs. The Crossbar skips selected pins as if they were already assigned, and moves to the next unassigned pin. Figure 20.3 shows the Crossbar Decoder priority with no Port pins skipped (P0SKIP, P1SKIP = 0x00); Figure 20.4 shows the Crossbar Decoder priority with the XTAL1 (P0.2) and XTAL2 (P0.3) pins skipped (P0SKIP = 0x0C). P0 SF Signals PIN I/O TX0 RX0 SCK MISO MOSI NSS 1 SDA SCL CP0 CP0A SYSCLK CEX0 CEX1 CEX2 ECI T0 T1 0 0 0 0 0 0 0 0 0 0 0 0 VREF IDA 0 1 x1 2 x2 3 4 5 CNVSTR 6 7 0 1 2 3 P1 4 5 6 7 0 12 P2 22 32 42 0 0 0 0 0 0 0 0 P0SKIP[0:7] Port pin potentially available to peripheral SF Signals Special Function Signals are not assigned by the crossbar. When these signals are enabled, the CrossBar must be manually configured to skip their corresponding port pins. P1SKIP[0:7] P2SKIP[0:3] Notes: 1. NSS is only pinned out in 4-wire SPI Mode 2. Pins P2.1-P2.4 only on QFN24 Package Figure 20.3. Crossbar Priority Decoder with No Pins Skipped Rev. 0.2 Pin not available for crossbar peripherals. 131 C8051F336/7/8/9 P0 S F S igna ls P IN I/O TX 0 RX 0 S CK M IS O M OS I NS S 1 S DA S CL CP 0 CP 0A S YS CLK CEX 0 CEX 1 CEX 2 ECI T0 T1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P 0S KIP [0:7] P ort pin potentially available to peripheral S F S igna ls S pec ial Func tion S ignals are not as s igned by the c ros s bar. W hen thes e s ignals are enabled, the Cros s B ar m us t be m anually c onfigured to s k ip their c orres ponding port pins . P 1S KIP [0:7] P 2S KIP [0:3 V REF IDA 0 1 x1 2 x2 3 4 5 CNV S TR 6 7 0 1 2 3 4 5 6 7 0 1 2 P1 P2 2 2 Notes : 1. NS S is only pinned out in 4-wire S P I M ode 2. P ins P 2.1-P 2.4 only on QFN24 P ac k age Figure 20.4. Crossbar Priority Decoder with Crystal Pins Skipped Registers XBR0 and XBR1 are used to assign the digital I/O resources to the physical I/O Port pins. Note that when the SMBus is selected, the Crossbar assigns both pins associated with the SMBus (SDA and SCL); when the UART is selected, the Crossbar assigns both pins associated with the UART (TX and RX). UART0 pin assignments are fixed for bootloading purposes: UART TX0 is always assigned to P0.4; UART RX0 is always assigned to P0.5. Standard Port I/Os appear contiguously after the prioritized functions have been assigned. Important Note: The SPI can be operated in either 3-wire or 4-wire modes, pending the state of the NSSMD1-NSSMD0 bits in register SPI0CN. According to the SPI mode, the NSS signal may or may not be routed to a Port pin. 132 Rev. 0.2 C8051F336/7/8/9 20.4. Port I/O Initialization Port I/O initialization consists of the following steps: Step 1. Select the input mode (analog or digital) for all Port pins, using the Port Input Mode register (PnMDIN). Step 2. Select the output mode (open-drain or push-pull) for all Port pins, using the Port Output Mode register (PnMDOUT). Step 3. Select any pins to be skipped by the I/O Crossbar using the Port Skip registers (PnSKIP). Step 4. Assign Port pins to desired peripherals. Step 5. Enable the Crossbar (XBARE = `1'). All Port pins must be configured as either analog or digital inputs. Any pins to be used as Comparator or ADC inputs should be configured as an analog inputs. When a pin is configured as an analog input, its weak pullup, digital driver, and digital receiver are disabled. This process saves power and reduces noise on the analog input. Pins configured as digital inputs may still be used by analog peripherals; however this practice is not recommended. Additionally, all analog input pins should be configured to be skipped by the Crossbar (accomplished by setting the associated bits in PnSKIP). Port input mode is set in the PnMDIN register, where a `1' indicates a digital input, and a `0' indicates an analog input. All pins default to digital inputs on reset. See SFR Definition 20.8 for the PnMDIN register details. The output driver characteristics of the I/O pins are defined using the Port Output Mode registers (PnMDOUT). Each Port Output driver can be configured as either open drain or push-pull. This selection is required even for the digital resources selected in the XBRn registers, and is not automatic. The only exception to this is the SMBus (SDA, SCL) pins, which are configured as open-drain regardless of the PnMDOUT settings. When the WEAKPUD bit in XBR1 is `0', a weak pullup is enabled for all Port I/O configured as open-drain. WEAKPUD does not affect the push-pull Port I/O. Furthermore, the weak pullup is turned off on an output that is driving a `0' to avoid unnecessary power dissipation. Registers XBR0 and XBR1 must be loaded with the appropriate values to select the digital I/O functions required by the design. Setting the XBARE bit in XBR1 to `1' enables the Crossbar. Until the Crossbar is enabled, the external pins remain as standard Port I/O (in input mode), regardless of the XBRn Register settings. For given XBRn Register settings, one can determine the I/O pin-out using the Priority Decode Table; as an alternative, the Configuration Wizard utility of the Silicon Labs IDE software will determine the Port I/O pin-assignments based on the XBRn Register settings. The Crossbar must be enabled to use Port pins as standard Port I/O in output mode. Port output drivers are disabled while the Crossbar is disabled. Rev. 0.2 133 C8051F336/7/8/9 SFR Definition 20.1. XBR0: Port I/O Crossbar Register 0 Bit Name Type Reset R 0 R 0 7 6 5 CP0AE R/W 0 4 CP0E R/W 0 3 SYSCKE R/W 0 2 SMB0E R/W 0 1 SPI0E R/W 0 0 URT0E R/W 0 SFR Address = 0xE1 Bit Name 7:6 5 Function UNUSED Unused. Read = 00b; Write = Don't Care. CP0AE Comparator0 Asynchronous Output Enable. 0: Asynchronous CP0 unavailable at Port pin. 1: Asynchronous CP0 routed to Port pin. 4 CP0E Comparator0 Output Enable. 0: CP0 unavailable at Port pin. 1: CP0 routed to Port pin. 3 SYSCKE /SYSCLK Output Enable. 0: /SYSCLK unavailable at Port pin. 1: /SYSCLK output routed to Port pin. 2 SMB0E SMBus I/O Enable. 0: SMBus I/O unavailable at Port pins. 1: SMBus I/O routed to Port pins. 1 SPI0E SPI I/O Enable. 0: SPI I/O unavailable at Port pins. 1: SPI I/O routed to Port pins. Note that the SPI can be assigned either 3 or 4 GPIO pins. 0 URT0E UART I/O Output Enable. 0: UART I/O unavailable at Port pin. 1: UART TX0, RX0 routed to Port pins P0.4 and P0.5. 134 Rev. 0.2 C8051F336/7/8/9 SFR Definition 20.2. XBR1: Port I/O Crossbar Register 1 Bit 7 6 XBARE R/W 0 5 T1E R/W 0 4 T0E R/W 0 3 ECIE R/W 0 R 0 2 1 0 Name WEAKPUD Type Reset R/W 0 PCA0ME[1:0] R/W 0 R/W 0 SFR Address = 0xE2 Bit Name 7 WEAKPUD Port I/O Weak Pullup Disable. Function 0: Weak Pullups enabled (except for Ports whose I/O are configured for analog mode). 1: Weak Pullups disabled. 6 XBARE Crossbar Enable. 0: Crossbar disabled. 1: Crossbar enabled. 5 T1E T1 Enable. 0: T1 unavailable at Port pin. 1: T1 routed to Port pin. 4 T0E T0 Enable. 0: T0 unavailable at Port pin. 1: T0 routed to Port pin. 3 ECIE PCA0 External Counter Input Enable. 0: ECI unavailable at Port pin. 1: ECI routed to Port pin. 2 UNUSED Unused. Read = 0b; Write = Don't Care. 00: All PCA I/O unavailable at Port pins. 01: CEX0 routed to Port pin. 10: CEX0, CEX1 routed to Port pins. 11: CEX0, CEX1, CEX2 routed to Port pins. 1:0 PCA0ME[1:0] PCA Module I/O Enable Bits. Rev. 0.2 135 C8051F336/7/8/9 20.5. Port Match Port match functionality allows system events to be triggered by a logic value change on P0 or P1. A software controlled value stored in the PnMATCH registers specifies the expected or normal logic values of P0 and P1. A Port mismatch event occurs if the logic levels of the Port's input pins no longer match the software controlled value. This allows Software to be notified if a certain change or pattern occurs on P0 or P1 input pins regardless of the XBRn settings. The PnMASK registers can be used to individually select which P0 and P1 pins should be compared against the PnMATCH registers. A Port mismatch event is generated if (P0 & P0MASK) does not equal (P0MATCH & P0MASK) or if (P1 & P1MASK) does not equal (P1MATCH & P1MASK). A Port mismatch event may be used to generate an interrupt or wake the device from a low power mode, such as IDLE or SUSPEND. See the Interrupts and Power Options chapters for more details on interrupt and wake-up sources. SFR Definition 20.3. P0MASK: Port 0 Mask Register Bit Name Type Reset 1 1 1 1 7 6 5 4 3 2 1 0 P0MASK[7:0] R/W 1 1 1 1 SFR Address = 0xFE Bit Name 7:0 P0MASK[7:0] Port 0 Mask Value. Function Selects P0 pins to be compared to the corresponding bits in P0MAT. 0: P0.n pin logic value is ignored and cannot cause a Port Mismatch event. 1: P0.n pin logic value is compared to P0MAT.n. SFR Definition 20.4. P0MAT: Port 0 Match Register Bit Name Type Reset 0 0 0 0 7 6 5 4 3 2 1 0 P0MAT[7:0] R/W 0 0 0 0 SFR Address = 0xFD Bit Name 7:0 P0MAT[7:0] Port 0 Match Value. Function Match comparison value used on Port 0 for bits in P0MAT which are set to `1'. 0: P0.n pin logic value is compared with logic LOW. 1: P0.n pin logic value is compared with logic HIGH. 136 Rev. 0.2 C8051F336/7/8/9 SFR Definition 20.5. P1MASK: Port 1 Mask Register Bit Name Type Reset 1 1 1 1 7 6 5 4 3 2 1 0 P1MASK[7:0] R/W 1 1 1 1 SFR Address = 0xEE Bit Name 7:0 P1MASK[7:0] Port 1 Mask Value. Function Selects P1 pins to be compared to the corresponding bits in P1MAT. 0: P1.n pin logic value is ignored and cannot cause a Port Mismatch event. 1: P1.n pin logic value is compared to P1MAT.n. SFR Definition 20.6. P1MAT: Port 1 Match Register Bit Name Type Reset 0 0 0 0 7 6 5 4 3 2 1 0 P1MAT[7:0] R/W 0 0 0 0 SFR Address = 0xED Bit Name 7:0 P1MAT[7:0] Port 1 Match Value. Function Match comparison value used on Port 1 for bits in P1MAT which are set to `1'. 0: P1.n pin logic value is compared with logic LOW. 1: P1.n pin logic value is compared with logic HIGH. Rev. 0.2 137 C8051F336/7/8/9 20.6. Special Function Registers for Accessing and Configuring Port I/O All Port I/O are accessed through corresponding special function registers (SFRs) that are both byte addressable and bit addressable. When writing to a Port, the value written to the SFR is latched to maintain the output data value at each pin. When reading, the logic levels of the Port's input pins are returned regardless of the XBRn settings (i.e., even when the pin is assigned to another signal by the Crossbar, the Port register can always read its corresponding Port I/O pin). The exception to this is the execution of the read-modify-write instructions that target a Port Latch register as the destination. The read-modify-write instructions when operating on a Port SFR are the following: ANL, ORL, XRL, JBC, CPL, INC, DEC, DJNZ and MOV, CLR or SETB, when the destination is an individual bit in a Port SFR. For these instructions, the value of the latch register (not the pin) is read, modified, and written back to the SFR. Each Port has a corresponding PnSKIP register which allows its individual Port pins to be assigned to digital functions or skipped by the Crossbar. All Port pins used for analog functions, GPIO, or dedicated digital functions such as the EMIF should have their PnSKIP bit set to `1'. The Port input mode of the I/O pins is defined using the Port Input Mode registers (PnMDIN). Each Port cell can be configured for analog or digital I/O. This selection is required even for the digital resources selected in the XBRn registers, and is not automatic. The only exception to this is P2.4, which can only be used for digital I/O. The output driver characteristics of the I/O pins are defined using the Port Output Mode registers (PnMDOUT). Each Port Output driver can be configured as either open drain or push-pull. This selection is required even for the digital resources selected in the XBRn registers, and is not automatic. The only exception to this is the SMBus (SDA, SCL) pins, which are configured as open-drain regardless of the PnMDOUT settings. SFR Definition 20.7. P0: Port 0 Bit Name Type Reset 1 1 1 1 7 6 5 4 P0[7:0] R/W 1 1 1 1 3 2 1 0 SFR Address = 0x80 Bit Name 7:0 P0[7:0] Description Write 0: Set output latch to logic LOW. 1: Set output latch to logic HIGH. Read 0: P0.n Port pin is logic LOW. 1: P0.n Port pin is logic HIGH. Port 0 Data. Sets the Port latch logic value or reads the Port pin logic state in Port cells configured for digital I/O. 138 Rev. 0.2 C8051F336/7/8/9 SFR Definition 20.8. P0MDIN: Port 0 Input Mode Bit Name Type Reset 1 1 1 1 7 6 5 4 3 2 1 0 P0MDIN[7:0] R/W 1 1 1 1 SFR Address = 0xF1 Bit Name 7:0 P0MDIN[7:0] Function Analog Configuration Bits for P0.7-P0.0 (respectively). Port pins configured for analog mode have their weak pullup, digital driver, and digital receiver disabled. 0: Corresponding P0.n pin is configured for analog mode. 1: Corresponding P0.n pin is not configured for analog mode. SFR Definition 20.9. P0MDOUT: Port 0 Output Mode Bit Name Type Reset 0 0 0 0 7 6 5 4 3 2 1 0 P0MDOUT[7:0] R/W 0 0 0 0 SFR Address = 0xA4 Bit Name Function These bits are ignored if the corresponding bit in register P0MDIN is logic 0. 0: Corresponding P0.n Output is open-drain. 1: Corresponding P0.n Output is push-pull. 7:0 P0MDOUT[7:0] Output Configuration Bits for P0.7-P0.0 (respectively). Rev. 0.2 139 C8051F336/7/8/9 SFR Definition 20.10. P0SKIP: Port 0 Skip Bit Name Type Reset 0 0 0 0 7 6 5 4 3 2 1 0 P0SKIP[7:0] R/W 0 0 0 0 SFR Address = 0xD4 Bit Name 7:0 P0SKIP[7:0] Port 0 Crossbar Skip Enable Bits. Function These bits select Port 0 pins to be skipped by the Crossbar Decoder. Port pins used for analog, special functions or GPIO should be skipped by the Crossbar. 0: Corresponding P0.n pin is not skipped by the Crossbar. 1: Corresponding P0.n pin is skipped by the Crossbar. SFR Definition 20.11. P1: Port 1 Bit Name Type Reset 1 1 1 1 7 6 5 4 P1[7:0] R/W 1 1 1 1 3 2 1 0 SFR Address = 0x90 Bit Name 7:0 P1[7:0] Description Write 0: Set output latch to logic LOW. 1: Set output latch to logic HIGH. Read 0: P1.n Port pin is logic LOW. 1: P1.n Port pin is logic HIGH. Port 1 Data. Sets the Port latch logic value or reads the Port pin logic state in Port cells configured for digital I/O. 140 Rev. 0.2 C8051F336/7/8/9 SFR Definition 20.12. P1MDIN: Port 1 Input Mode Bit Name Type Reset 1 1 1 1 7 6 5 4 3 2 1 0 P1MDIN[7:0] R/W 1 1 1 1 SFR Address = 0xF2 Bit Name 7:0 P1MDIN[7:0] Function Analog Configuration Bits for P1.7-P1.0 (respectively). Port pins configured for analog mode have their weak pullup, digital driver, and digital receiver disabled. 0: Corresponding P1.n pin is configured for analog mode. 1: Corresponding P1.n pin is not configured for analog mode. SFR Definition 20.13. P1MDOUT: Port 1 Output Mode Bit Name Type Reset 0 0 0 0 7 6 5 4 3 2 1 0 P1MDOUT[7:0] R/W 0 0 0 0 SFR Address = 0xA5 Bit Name Function These bits are ignored if the corresponding bit in register P1MDIN is logic 0. 0: Corresponding P1.n Output is open-drain. 1: Corresponding P1.n Output is push-pull. 7:0 P1MDOUT[7:0] Output Configuration Bits for P1.7-P1.0 (respectively). Rev. 0.2 141 C8051F336/7/8/9 SFR Definition 20.14. P1SKIP: Port 1 Skip Bit Name Type Reset 0 0 0 0 7 6 5 4 3 2 1 0 P1SKIP[7:0] R/W 0 0 0 0 SFR Address = 0xD5 Bit Name 7:0 P1SKIP[7:0] Port 1 Crossbar Skip Enable Bits. Function These bits select Port 1 pins to be skipped by the Crossbar Decoder. Port pins used for analog, special functions or GPIO should be skipped by the Crossbar. 0: Corresponding P1.n pin is not skipped by the Crossbar. 1: Corresponding P1.n pin is skipped by the Crossbar. SFR Definition 20.15. P2: Port 2 Bit Name Type Reset R 0 R 0 R 0 1 1 7 6 5 4 3 2 P2[4:0] R/W 1 1 1 1 0 SFR Address = 0xA0 Bit Name 7:5 4:0 Description Write Don't Care 0: Set output latch to logic LOW. 1: Set output latch to logic HIGH. 000b Read UNUSED Unused. P2[4:0] Port 2 Data. Sets the Port latch logic value or reads the Port pin logic state in Port cells configured for digital I/O. 0: P2.n Port pin is logic LOW. 1: P2.n Port pin is logic HIGH. Note: Pins P2.1-P2.4 are only available in QFN24-packaged devices. 142 Rev. 0.2 C8051F336/7/8/9 SFR Definition 20.16. P2MDIN: Port 2 Input Mode Bit Name Type Reset R 0 R 0 R 0 R 0 1 1 7 6 5 4 3 2 1 0 P2MDIN[7:0] R/W 1 1 SFR Address = 0xF3 Bit Name 7:4 3:0 UNUSED P2MDIN[3:0] Function Unused. Read = 0000b; Write = Don't Care Analog Configuration Bits for P2.3-P2.0 (respectively). Port pins configured for analog mode have their weak pullup, digital driver, and digital receiver disabled. 0: Corresponding P2.n pin is configured for analog mode. 1: Corresponding P2.n pin is not configured for analog mode. Note: Pins P2.1-P2.4 are only available in QFN24-packaged devices. SFR Definition 20.17. P2MDOUT: Port 2 Output Mode Bit Name Type Reset R 0 R 0 R 0 0 0 7 6 5 4 3 2 P2MDOUT[4:0] R/W 0 0 0 1 0 SFR Address = 0xA6 Bit Name 7:5 UNUSED Function Unused. Read = 000b; Write = Don't Care These bits are ignored if the corresponding bit in register P2MDIN is logic 0. 0: Corresponding P2.n Output is open-drain. 1: Corresponding P2.n Output is push-pull. 4:0 P2MDOUT[4:0] Output Configuration Bits for P2.4-P2.0 (respectively). Note: Pins P2.1-P2.4 are only available in QFN24-packaged devices. Rev. 0.2 143 C8051F336/7/8/9 SFR Definition 20.18. P2SKIP: Port 2 Skip Bit Name Type Reset R 0 R 0 R 0 R 0 0 0 7 6 5 4 3 2 1 0 P2SKIP[7:0] R/W 0 0 SFR Address = 0xD6 Bit Name 7:4 3:0 UNUSED P2SKIP[3:0] Function Unused. Read = 0000b; Write = Don't Care Port 2 Crossbar Skip Enable Bits. These bits select Port 2 pins to be skipped by the Crossbar Decoder. Port pins used for analog, special functions or GPIO should be skipped by the Crossbar. 0: Corresponding P2.n pin is not skipped by the Crossbar. 1: Corresponding P2.n pin is skipped by the Crossbar. Note: Pins P2.1-P2.4 are only available in QFN24-packaged devices. 144 Rev. 0.2 C8051F336/7/8/9 21. SMBus The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System Management Bus Specification, version 1.1, and compatible with the I2C serial bus. Reads and writes to the interface by the system controller are byte oriented with the SMBus interface autonomously controlling the serial transfer of the data. Data can be transferred at up to 1/20th of the system clock as a master or slave (this can be faster than allowed by the SMBus specification, depending on the system clock used). A method of extending the clock-low duration is available to accommodate devices with different speed capabilities on the same bus. The SMBus interface may operate as a master and/or slave, and may function on a bus with multiple masters. The SMBus provides control of SDA (serial data), SCL (serial clock) generation and synchronization, arbitration logic, and START/STOP control and generation. The SMBus peripheral can be fully driven by software (i.e. software accepts/rejects slave addresses, and generates ACKs), or hardware slave address recognition and automatic ACK generation can be enabled to minimize software overhead. A block diagram of the SMBus peripheral and the associated SFRs is shown in Figure 21.1. SMB0CN MTSSAAAS AXTTCRC I SMAOKBK TO RL ED QO RE S T SMB0CF E I BESSSS N N U XMMMM SHSTBBBB M YHTFCC B OOT S S LEE10 D 00 01 10 11 SMBUS CONTROL LOGIC Arbitration SCL Synchronization SCL Generation (Master Mode) SDA Control Hardware Slave Address Recognition Hardware ACK Generation Data Path IRQ Generation Control T0 Overflow T1 Overflow TMR2H Overflow TMR2L Overflow SCL FILTER Interrupt Request SCL Control N SDA Control C R O S S B A R SDA Port I/O SMB0DAT 76543210 S L V 6 S L V 5 S L V 4 S L V 3 S L V 2 S L V 1 SG LC V 0 SSSSSSS LLLLLLL VVVVVVV MMMMMMM 6543210 SMB0ADM E H A C K FILTER SMB0ADR N Figure 21.1. SMBus Block Diagram 21.1. Supporting Documents It is assumed the reader is familiar with or has access to the following supporting documents: Rev. 0.2 145 C8051F336/7/8/9 1. The I2C-Bus and How to Use It (including specifications), Philips Semiconductor. 2. The I2C-Bus Specification--Version 2.0, Philips Semiconductor. 3. System Management Bus Specification--Version 1.1, SBS Implementers Forum. 21.2. SMBus Configuration Figure 21.2 shows a typical SMBus configuration. The SMBus specification allows any recessive voltage between 3.0 V and 5.0 V; different devices on the bus may operate at different voltage levels. The bi-directional SCL (serial clock) and SDA (serial data) lines must be connected to a positive power supply voltage through a pullup resistor or similar circuit. Every device connected to the bus must have an open-drain or open-collector output for both the SCL and SDA lines, so that both are pulled high (recessive state) when the bus is free. The maximum number of devices on the bus is limited only by the requirement that the rise and fall times on the bus not exceed 300 ns and 1000 ns, respectively. VDD = 5V VDD = 3V VDD = 5V VDD = 3V Master Device Slave Device 1 Slave Device 2 SDA SCL Figure 21.2. Typical SMBus Configuration 21.3. SMBus Operation Two types of data transfers are possible: data transfers from a master transmitter to an addressed slave receiver (WRITE), and data transfers from an addressed slave transmitter to a master receiver (READ). The master device initiates both types of data transfers and provides the serial clock pulses on SCL. The SMBus interface may operate as a master or a slave, and multiple master devices on the same bus are supported. If two or more masters attempt to initiate a data transfer simultaneously, an arbitration scheme is employed with a single master always winning the arbitration. Note that it is not necessary to specify one device as the Master in a system; any device who transmits a START and a slave address becomes the master for the duration of that transfer. A typical SMBus transaction consists of a START condition followed by an address byte (Bits7-1: 7-bit slave address; Bit0: R/W direction bit), one or more bytes of data, and a STOP condition. Bytes that are received (by a master or slave) are acknowledged (ACK) with a low SDA during a high SCL (see Figure 21.3). If the receiving device does not ACK, the transmitting device will read a NACK (not acknowledge), which is a high SDA during a high SCL. The direction bit (R/W) occupies the least-significant bit position of the address byte. The direction bit is set to logic 1 to indicate a "READ" operation and cleared to logic 0 to indicate a "WRITE" operation. All transactions are initiated by a master, with one or more addressed slave devices as the target. The master generates the START condition and then transmits the slave address and direction bit. If the trans- 146 Rev. 0.2 C8051F336/7/8/9 action is a WRITE operation from the master to the slave, the master transmits the data a byte at a time waiting for an ACK from the slave at the end of each byte. For READ operations, the slave transmits the data waiting for an ACK from the master at the end of each byte. At the end of the data transfer, the master generates a STOP condition to terminate the transaction and free the bus. Figure 21.3 illustrates a typical SMBus transaction. SCL SDA SLA6 SLA5-0 R/W D7 D6-0 START Slave Address + R/W ACK Data Byte NACK STOP Figure 21.3. SMBus Transaction 21.3.1. Transmitter Vs. Receiver On the SMBus communications interface, a device is the "transmitter" when it is sending an address or data byte to another device on the bus. A device is a "receiver" when an address or data byte is being sent to it from another device on the bus. The transmitter controls the SDA line during the address or data byte. After each byte of address or data information is sent by the transmitter, the receiver sends an ACK or NACK bit during the ACK phase of the transfer, during which time the receiver controls the SDA line. 21.3.2. Arbitration A master may start a transfer only if the bus is free. The bus is free after a STOP condition or after the SCL and SDA lines remain high for a specified time (see Section "21.3.5. SCL High (SMBus Free) Timeout" on page 148). In the event that two or more devices attempt to begin a transfer at the same time, an arbitration scheme is employed to force one master to give up the bus. The master devices continue transmitting until one attempts a HIGH while the other transmits a LOW. Since the bus is open-drain, the bus will be pulled LOW. The master attempting the HIGH will detect a LOW SDA and lose the arbitration. The winning master continues its transmission without interruption; the losing master becomes a slave and receives the rest of the transfer if addressed. This arbitration scheme is non-destructive: one device always wins, and no data is lost. Rev. 0.2 147 C8051F336/7/8/9 21.3.3. Clock Low Extension SMBus provides a clock synchronization mechanism, similar to I2C, which allows devices with different speed capabilities to coexist on the bus. A clock-low extension is used during a transfer in order to allow slower slave devices to communicate with faster masters. The slave may temporarily hold the SCL line LOW to extend the clock low period, effectively decreasing the serial clock frequency. 21.3.4. SCL Low Timeout If the SCL line is held low by a slave device on the bus, no further communication is possible. Furthermore, the master cannot force the SCL line high to correct the error condition. To solve this problem, the SMBus protocol specifies that devices participating in a transfer must detect any clock cycle held low longer than 25 ms as a "timeout" condition. Devices that have detected the timeout condition must reset the communication no later than 10 ms after detecting the timeout condition. When the SMBTOE bit in SMB0CF is set, Timer 3 is used to detect SCL low timeouts. Timer 3 is forced to reload when SCL is high, and allowed to count when SCL is low. With Timer 3 enabled and configured to overflow after 25 ms (and SMBTOE set), the Timer 3 interrupt service routine can be used to reset (disable and re-enable) the SMBus in the event of an SCL low timeout. 21.3.5. SCL High (SMBus Free) Timeout The SMBus specification stipulates that if the SCL and SDA lines remain high for more that 50 s, the bus is designated as free. When the SMBFTE bit in SMB0CF is set, the bus will be considered free if SCL and SDA remain high for more than 10 SMBus clock source periods (as defined by the timer configured for the SMBus clock source). If the SMBus is waiting to generate a Master START, the START will be generated following this timeout. Note that a clock source is required for free timeout detection, even in a slave-only implementation. 21.4. Using the SMBus The SMBus can operate in both Master and Slave modes. The interface provides timing and shifting control for serial transfers; higher level protocol is determined by user software. The SMBus interface provides the following application-independent features: * * * * * * * * Byte-wise serial data transfers Clock signal generation on SCL (Master Mode only) and SDA data synchronization Timeout/bus error recognition, as defined by the SMB0CF configuration register START/STOP timing, detection, and generation Bus arbitration Interrupt generation Status information Optional hardware recognition of slave address and automatic acknowledgement of address/data SMBus interrupts are generated for each data byte or slave address that is transferred. When hardware acknowledgement is disabled, the point at which the interrupt is generated depends on whether the hardware is acting as a data transmitter or receiver. When a transmitter (i.e. sending address/data, receiving an ACK), this interrupt is generated after the ACK cycle so that software may read the received ACK value; when receiving data (i.e. receiving address/data, sending an ACK), this interrupt is generated before the ACK cycle so that software may define the outgoing ACK value. If hardware acknowledgement is enabled, these interrupts are always generated after the ACK cycle. See Section 21.5 for more details on transmission sequences. 148 Rev. 0.2 C8051F336/7/8/9 Interrupts are also generated to indicate the beginning of a transfer when a master (START generated), or the end of a transfer when a slave (STOP detected). Software should read the SMB0CN (SMBus Control register) to find the cause of the SMBus interrupt. The SMB0CN register is described in Section 21.4.2; Table 21.5 provides a quick SMB0CN decoding reference. 21.4.1. SMBus Configuration Register The SMBus Configuration register (SMB0CF) is used to enable the SMBus Master and/or Slave modes, select the SMBus clock source, and select the SMBus timing and timeout options. When the ENSMB bit is set, the SMBus is enabled for all master and slave events. Slave events may be disabled by setting the INH bit. With slave events inhibited, the SMBus interface will still monitor the SCL and SDA pins; however, the interface will NACK all received addresses and will not generate any slave interrupts. When the INH bit is set, all slave events will be inhibited following the next START (interrupts will continue for the duration of the current transfer). Table 21.1. SMBus Clock Source Selection SMBCS1 0 0 1 1 SMBCS0 0 1 0 1 SMBus Clock Source Timer 0 Overflow Timer 1 Overflow Timer 2 High Byte Overflow Timer 2 Low Byte Overflow The SMBCS1-0 bits select the SMBus clock source, which is used only when operating as a master or when the Free Timeout detection is enabled. When operating as a master, overflows from the selected source determine the absolute minimum SCL low and high times as defined in Equation 21.1. Note that the selected clock source may be shared by other peripherals so long as the timer is left running at all times. For example, Timer 1 overflows may generate the SMBus and UART baud rates simultaneously. Timer configuration is covered in Section "24. Timers" on page 187. 1 T HighMin = T LowMin = --------------------------------------------f ClockSourceOverflow Equation 21.1. Minimum SCL High and Low Times The selected clock source should be configured to establish the minimum SCL High and Low times as per Equation 21.1. When the interface is operating as a master (and SCL is not driven or extended by any other devices on the bus), the typical SMBus bit rate is approximated by Equation 21.2. f ClockSourceOverflow BitRate = --------------------------------------------3 Equation 21.2. Typical SMBus Bit Rate Rev. 0.2 149 C8051F336/7/8/9 Figure 21.4 shows the typical SCL generation described by Equation 21.2. Notice that THIGH is typically twice as large as TLOW. The actual SCL output may vary due to other devices on the bus (SCL may be extended low by slower slave devices, or driven low by contending master devices). The bit rate when operating as a master will never exceed the limits defined by equation Equation 21.1. Timer Source Overflows SCL TLow THigh SCL High Timeout Figure 21.4. Typical SMBus SCL Generation Setting the EXTHOLD bit extends the minimum setup and hold times for the SDA line. The minimum SDA setup time defines the absolute minimum time that SDA is stable before SCL transitions from low-to-high. The minimum SDA hold time defines the absolute minimum time that the current SDA value remains stable after SCL transitions from high-to-low. EXTHOLD should be set so that the minimum setup and hold times meet the SMBus Specification requirements of 250 ns and 300 ns, respectively. Table 21.2 shows the minimum setup and hold times for the two EXTHOLD settings. Setup and hold time extensions are typically necessary when SYSCLK is above 10 MHz. Table 21.2. Minimum SDA Setup and Hold Times EXTHOLD 0 1 Minimum SDA Setup Time Tlow - 4 system clocks or 1 system clock + s/w delay* 11 system clocks Minimum SDA Hold Time 3 system clocks 12 system clocks *Note: Setup Time for ACK bit transmissions and the MSB of all data transfers. When using software acknowledgement, the s/w delay occurs between the time SMB0DAT or ACK is written and when SI is cleared. Note that if SI is cleared in the same write that defines the outgoing ACK value, s/w delay is zero. With the SMBTOE bit set, Timer 3 should be configured to overflow after 25 ms in order to detect SCL low timeouts (see Section "21.3.4. SCL Low Timeout" on page 148). The SMBus interface will force Timer 3 to reload while SCL is high, and allow Timer 3 to count when SCL is low. The Timer 3 interrupt service routine should be used to reset SMBus communication by disabling and re-enabling the SMBus. SMBus Free Timeout detection can be enabled by setting the SMBFTE bit. When this bit is set, the bus will be considered free if SDA and SCL remain high for more than 10 SMBus clock source periods (see Figure 21.4). 150 Rev. 0.2 C8051F336/7/8/9 SFR Definition 21.1. SMB0CF: SMBus Clock/Configuration Bit Name Type Reset 7 ENSMB R/W 0 6 INH R/W 0 5 BUSY R 0 4 3 2 SMBFTE R/W 0 0 1 0 EXTHOLD SMBTOE R/W 0 R/W 0 SMBCS[1:0] R/W 0 SFR Address = 0xC1 Bit Name 7 ENSMB SMBus Enable. Function This bit enables the SMBus interface when set to `1'. When enabled, the interface constantly monitors the SDA and SCL pins. 6 INH SMBus Slave Inhibit. When this bit is set to logic 1, the SMBus does not generate an interrupt when slave events occur. This effectively removes the SMBus slave from the bus. Master Mode interrupts are not affected. 5 BUSY SMBus Busy Indicator. This bit is set to logic 1 by hardware when a transfer is in progress. It is cleared to logic 0 when a STOP or free-timeout is sensed. 4 EXTHOLD SMBus Setup and Hold Time Extension Enable. This bit controls the SDA setup and hold times according to Table 21.2. 0: SDA Extended Setup and Hold Times disabled. 1: SDA Extended Setup and Hold Times enabled. 3 SMBTOE SMBus SCL Timeout Detection Enable. This bit enables SCL low timeout detection. If set to logic 1, the SMBus forces Timer 3 to reload while SCL is high and allows Timer 3 to count when SCL goes low. If Timer 3 is configured to Split Mode, only the High Byte of the timer is held in reload while SCL is high. Timer 3 should be programmed to generate interrupts at 25 ms, and the Timer 3 interrupt service routine should reset SMBus communication. 2 SMBFTE SMBus Free Timeout Detection Enable. When this bit is set to logic 1, the bus will be considered free if SCL and SDA remain high for more than 10 SMBus clock source periods. 1:0 SMBCS[1:0] SMBus Clock Source Selection. These two bits select the SMBus clock source, which is used to generate the SMBus bit rate. The selected device should be configured according to Equation 21.1. 00: Timer 0 Overflow 01: Timer 1 Overflow 10 :Timer 2 High Byte Overflow 11: Timer 2 Low Byte Overflow Rev. 0.2 151 C8051F336/7/8/9 21.4.2. SMB0CN Control Register SMB0CN is used to control the interface and to provide status information (see SFR Definition 21.2). The higher four bits of SMB0CN (MASTER, TXMODE, STA, and STO) form a status vector that can be used to jump to service routines. MASTER indicates whether a device is the master or slave during the current transfer. TXMODE indicates whether the device is transmitting or receiving data for the current byte. STA and STO indicate that a START and/or STOP has been detected or generated since the last SMBus interrupt. STA and STO are also used to generate START and STOP conditions when operating as a master. Writing a `1' to STA will cause the SMBus interface to enter Master Mode and generate a START when the bus becomes free (STA is not cleared by hardware after the START is generated). Writing a `1' to STO while in Master Mode will cause the interface to generate a STOP and end the current transfer after the next ACK cycle. If STO and STA are both set (while in Master Mode), a STOP followed by a START will be generated. The ARBLOST bit indicates that the interface has lost an arbitration. This may occur anytime the interface is transmitting (master or slave). A lost arbitration while operating as a slave indicates a bus error condition. ARBLOST is cleared by hardware each time SI is cleared. The SI bit (SMBus Interrupt Flag) is set at the beginning and end of each transfer, after each byte frame, or when an arbitration is lost; see Table 21.3 for more details. Important Note About the SI Bit: The SMBus interface is stalled while SI is set; thus SCL is held low, and the bus is stalled until software clears SI. 21.4.2.1.Software ACK Generation When the EHACK bit in register SMB0ADM is cleared to `0', the firmware on the device must detect incoming slave addresses and ACK or NACK the slave address and incoming data bytes. As a receiver, writing the ACK bit defines the outgoing ACK value; as a transmitter, reading the ACK bit indicates the value received during the last ACK cycle. ACKRQ is set each time a byte is received, indicating that an outgoing ACK value is needed. When ACKRQ is set, software should write the desired outgoing value to the ACK bit before clearing SI. A NACK will be generated if software does not write the ACK bit before clearing SI. SDA will reflect the defined ACK value immediately following a write to the ACK bit; however SCL will remain low until SI is cleared. If a received slave address is not acknowledged, further slave events will be ignored until the next START is detected. 21.4.2.2.Hardware ACK Generation When the EHACK bit in register SMB0ADM is set to `1', automatic slave address recognition and ACK generation is enabled. More detail about automatic slave address recognition can be found in Section 21.4.3. As a receiver, the value currently specified by the ACK bit will be automatically sent on the bus during the ACK cycle of an incoming data byte. As a transmitter, reading the ACK bit indicates the value received on the last ACK cycle. The ACKRQ bit is not used when hardware ACK generation is enabled. If a received slave address is NACKed by hardware, further slave events will be ignored until the next START is detected, and no interrupt will be generated. Table 21.3 lists all sources for hardware changes to the SMB0CN bits. Refer to Table 21.5 for SMBus status decoding using the SMB0CN register. 152 Rev. 0.2 C8051F336/7/8/9 SFR Definition 21.2. SMB0CN: SMBus Control Bit Name Type Reset 7 MASTER R 0 6 TXMODE R 0 5 STA R/W 0 4 STO R/W 0 3 ACKRQ R 0 2 ARBLOST R 0 1 ACK R/W 0 0 SI R/W 0 SFR Address = 0xC0; Bit-Addressable Bit Name Description 7 MASTER SMBus Master/Slave Indicator. This read-only bit indicates when the SMBus is operating as a master. TXMODE SMBus Transmit Mode Indicator. This read-only bit indicates when the SMBus is operating as a transmitter. STA SMBus Start Flag. Read 0: SMBus operating in slave mode. 1: SMBus operating in master mode. 0: SMBus in Receiver Mode. 1: SMBus in Transmitter Mode. 0: No Start or repeated Start detected. 1: Start or repeated Start detected. 0: No Stop condition detected. 1: Stop condition detected (if in Slave Mode) or pending (if in Master Mode). N/A Write 6 N/A 5 0: No Start generated. 1: When Configured as a Master, initiates a START or repeated START. 0: No STOP condition is transmitted. 1: When configured as a Master, causes a STOP condition to be transmitted after the next ACK cycle. Cleared by Hardware. N/A N/A 0: Send NACK 1: Send ACK 0: Clear interrupt, and initiate next state machine event. 1: Force interrupt. 4 STO SMBus Stop Flag. 3 2 1 0 ACKRQ SMBus Acknowledge Request. 0: No Ack requested 1: ACK requested 0: No arbitration error. 1: Arbitration Lost 0: NACK received. 1: ACK received. ARBLOST SMBus Arbitration Lost Indicator. ACK SI SMBus Acknowledge. SMBus Interrupt Flag. 0: No interrupt pending This bit is set by hardware 1: Interrupt Pending under the conditions listed in Table 15.3. SI must be cleared by software. While SI is set, SCL is held low and the SMBus is stalled. Rev. 0.2 153 C8051F336/7/8/9 Table 21.3. Sources for Hardware Changes to SMB0CN Bit MASTER Set by Hardware When: * A START is generated. * START is generated. * SMB0DAT is written before the start of an SMBus frame. * A START followed by an address byte is received. * A STOP is detected while addressed as a slave. * Arbitration is lost due to a detected STOP. * A byte has been received and an ACK response value is needed (only when hardware ACK is not enabled). * A repeated START is detected as a MASTER when STA is low (unwanted repeated START). * SCL is sensed low while attempting to generate a STOP or repeated START condition. * SDA is sensed low while transmitting a `1' (excluding ACK bits). * The incoming ACK value is low (ACKNOWLEDGE). * A START has been generated. * Lost arbitration. * A byte has been transmitted and an ACK/NACK received. * A byte has been received. * A START or repeated START followed by a slave address + R/W has been received. * A STOP has been received. Cleared by Hardware When: * A STOP is generated. * Arbitration is lost. * A START is detected. * Arbitration is lost. * SMB0DAT is not written before the start of an SMBus frame. * Must be cleared by software. * A pending STOP is generated. TXMODE STA STO ACKRQ * After each ACK cycle. ARBLOST * Each time SI is cleared. ACK * The incoming ACK value is high (NOT ACKNOWLEDGE). SI * Must be cleared by software. 154 Rev. 0.2 C8051F336/7/8/9 21.4.3. Hardware Slave Address Recognition The SMBus hardware has the capability to automatically recognize incoming slave addresses and send an ACK without software intervention. Automatic slave address recognition is enabled by setting the EHACK bit in register SMB0ADM to `1'. This will enable both automatic slave address recognition and automatic hardware ACK generation for received bytes (as a master or slave). More detail on automatic hardware ACK generation can be found in Section 21.4.2.2. The registers used to define which address(es) are recognized by the hardware are the SMBus Slave Address register (SFR Definition 21.3) and the SMBus Slave Address Mask register (SFR Definition 21.4). A single address or range of addresses (including the General Call Address 0x00) can be specified using these two registers. The most-significant seven bits of the two registers are used to define which addresses will be ACKed. A `1' in bit positions of the slave address mask SLVM[6:0] enable a comparison between the received slave address and the hardware's slave address SLV[6:0] for those bits. A `0' in a bit of the slave address mask means that bit will be treated as a "don't care" for comparison purposes. In this case, either a `1' or a `0' value are acceptable on the incoming slave address. Additionally, if the GC bit in register SMB0ADR is set to `1', hardware will recognize the General Call Address (0x00). Table 21.4 shows some example parameter settings and the slave addresses that will be recognized by hardware under those conditions. Table 21.4. Hardware Address Recognition Examples (EHACK = 1) Hardware Slave Address SLV[6:0] 0x34 0x34 0x34 0x34 0x70 Slave Address Mask SLVM[6:0] 0x7F 0x7F 0x7E 0x7E 0x73 GC bit 0 1 0 1 0 Slave Addresses Recognized by Hardware 0x34 0x34, 0x00 (General Call) 0x34, 0x35 0x34, 0x35, 0x00 (General Call) 0x70, 0x74, 0x78, 0x7C Rev. 0.2 155 C8051F336/7/8/9 SFR Definition 21.3. SMB0ADR: SMBus Slave Address Bit Name Type Reset 0 0 0 7 6 5 4 SLV[6:0] R/W 0 0 0 0 3 2 1 0 GC R/W 0 SFR Address = 0xD7 Bit Name 7:1 SLV[6:0] SMBus Hardware Slave Address. Function Defines the SMBus Slave Address(es) for automatic hardware acknowledgement. Only address bits which have a `1' in the corresponding bit position in SLVM[6:0] are checked against the incoming address. This allows multiple addresses to be recognized. 0 GC General Call Address Enable. When hardware address recognition is enabled (EHACK = 1), this bit will determine whether the General Call Address (0x00) is also recognized by hardware. 0: General Call Address is ignored. 1: General Call Address is recognized. SFR Definition 21.4. SMB0ADM: SMBus Slave Address Mask Bit Name Type Reset 1 1 1 7 6 5 4 SLVM[6:0] R/W 1 1 1 1 3 2 1 0 EHACK R/W 0 SFR Address = 0xE7 Bit Name 7:1 SLVM[6:0] SMBus Slave Address Mask. Function Defines which bits of register SMB0ADR are compared with an incoming address byte, and which bits are ignored. Any bit set to `1' in SLVM[6:0] enables comparisons with the corresponding bit in SLV[6:0]. Bits set to `0' are ignored (can be either `0' or `1' in the incoming address). 0 EHACK Hardware Acknowledge Enable. Enables hardware acknowledgement of slave address and received data bytes. 0: Firmware must manually acknowledge all incoming address and data bytes. 1: Automatic Slave Address Recognition and Hardware Acknowledge is Enabled. 156 Rev. 0.2 C8051F336/7/8/9 21.4.4. Data Register The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been received. Software may safely read or write to the data register when the SI flag is set. Software should not attempt to access the SMB0DAT register when the SMBus is enabled and the SI flag is cleared to logic 0, as the interface may be in the process of shifting a byte of data into or out of the register. Data in SMB0DAT is always shifted out MSB first. After a byte has been received, the first bit of received data is located at the MSB of SMB0DAT. While data is being shifted out, data on the bus is simultaneously being shifted in. SMB0DAT always contains the last data byte present on the bus. In the event of lost arbitration, the transition from master transmitter to slave receiver is made with the correct data or address in SMB0DAT. SFR Definition 21.5. SMB0DAT: SMBus Data Bit Name Type Reset 0 0 0 0 7 6 5 4 3 2 1 0 SMB0DAT[7:0] R/W 0 0 0 0 SFR Address = 0xC2 Bit Name 7:0 SMB0DAT[7:0] SMBus Data. Function The SMB0DAT register contains a byte of data to be transmitted on the SMBus serial interface or a byte that has just been received on the SMBus serial interface. The CPU can read from or write to this register whenever the SI serial interrupt flag (SMB0CN.0) is set to logic 1. The serial data in the register remains stable as long as the SI flag is set. When the SI flag is not set, the system may be in the process of shifting data in/out and the CPU should not attempt to access this register. Rev. 0.2 157 C8051F336/7/8/9 21.5. SMBus Transfer Modes The SMBus interface may be configured to operate as master and/or slave. At any particular time, it will be operating in one of the following four modes: Master Transmitter, Master Receiver, Slave Transmitter, or Slave Receiver. The SMBus interface enters Master Mode any time a START is generated, and remains in Master Mode until it loses an arbitration or generates a STOP. An SMBus interrupt is generated at the end of all SMBus byte frames. Note that the position of the ACK interrupt when operating as a receiver depends on whether hardware ACK generation is enabled. As a receiver, the interrupt for an ACK occurs before the ACK with hardware ACK generation disabled, and after the ACK when hardware ACK generation is enabled. As a transmitter, interrupts occur after the ACK, regardless of whether hardware ACK generation is enabled or not. 21.5.1. Write Sequence (Master) During a write sequence, an SMBus master writes data to a slave device. The master in this transfer will be a transmitter during the address byte, and a transmitter during all data bytes. The SMBus interface generates the START condition and transmits the first byte containing the address of the target slave and the data direction bit. In this case the data direction bit (R/W) will be logic 0 (WRITE). The master then transmits one or more bytes of serial data. After each byte is transmitted, an acknowledge bit is generated by the slave. The transfer is ended when the STO bit is set and a STOP is generated. Note that the interface will switch to Master Receiver Mode if SMB0DAT is not written following a Master Transmitter interrupt. Figure 21.5 shows a typical master write sequence. Two transmit data bytes are shown, though any number of bytes may be transmitted. Notice that all of the `data byte transferred' interrupts occur after the ACK cycle in this mode, regardless of whether hardware ACK generation is enabled. Interrupts with Hardware ACK Enabled (EHACK = 1) S SLA W A Data Byte A Data Byte A P Interrupts with Hardware ACK Disabled (EHACK = 0) Received by SMBus Interface Transmitted by SMBus Interface S = START P = STOP A = ACK W = WRITE SLA = Slave Address Figure 21.5. Typical Master Write Sequence 158 Rev. 0.2 C8051F336/7/8/9 21.5.2. Read Sequence (Master) During a read sequence, an SMBus master reads data from a slave device. The master in this transfer will be a transmitter during the address byte, and a receiver during all data bytes. The SMBus interface generates the START condition and transmits the first byte containing the address of the target slave and the data direction bit. In this case the data direction bit (R/W) will be logic 1 (READ). Serial data is then received from the slave on SDA while the SMBus outputs the serial clock. The slave transmits one or more bytes of serial data. If hardware ACK generation is disabled, the ACKRQ is set to `1' and an interrupt is generated after each received byte. Software must write the ACK bit at that time to ACK or NACK the received byte. With hardware ACK generation enabled, the SMBus hardware will automatically generate the ACK/NACK, and then post the interrupt. It is important to note that the appropriate ACK or NACK value should be set up by the software prior to receiving the byte when hardware ACK generation is enabled. Writing a `1' to the ACK bit generates an ACK; writing a `0' generates a NACK. Software should write a `0' to the ACK bit for the last data transfer, to transmit a NACK. The interface exits Master Receiver Mode after the STO bit is set and a STOP is generated. The interface will switch to Master Transmitter Mode if SMB0DAT is written while an active Master Receiver. Figure 21.6 shows a typical master read sequence. Two received data bytes are shown, though any number of bytes may be received. Notice that the `data byte transferred' interrupts occur at different places in the sequence, depending on whether hardware ACK generation is enabled. The interrupt occurs before the ACK with hardware ACK generation disabled, and after the ACK when hardware ACK generation is enabled. Interrupts with Hardware ACK Enabled (EHACK = 1) S SLA R A Data Byte A Data Byte N P Interrupts with Hardware ACK Disabled (EHACK = 0) Received by SMBus Interface Transmitted by SMBus Interface S = START P = STOP A = ACK N = NACK R = READ SLA = Slave Address Figure 21.6. Typical Master Read Sequence Rev. 0.2 159 C8051F336/7/8/9 21.5.3. Write Sequence (Slave) During a write sequence, an SMBus master writes data to a slave device. The slave in this transfer will be a receiver during the address byte, and a receiver during all data bytes. When slave events are enabled (INH = 0), the interface enters Slave Receiver Mode when a START followed by a slave address and direction bit (WRITE in this case) is received. If hardware ACK generation is disabled, upon entering Slave Receiver Mode, an interrupt is generated and the ACKRQ bit is set. The software must respond to the received slave address with an ACK, or ignore the received slave address with a NACK. If hardware ACK generation is enabled, the hardware will apply the ACK for a slave address which matches the criteria set up by SMB0ADR and SMB0ADM. The interrupt will occur after the ACK cycle. If the received slave address is ignored (by software or hardware), slave interrupts will be inhibited until the next START is detected. If the received slave address is acknowledged, zero or more data bytes are received. If hardware ACK generation is disabled, the ACKRQ is set to `1' and an interrupt is generated after each received byte. Software must write the ACK bit at that time to ACK or NACK the received byte. With hardware ACK generation enabled, the SMBus hardware will automatically generate the ACK/NACK, and then post the interrupt. It is important to note that the appropriate ACK or NACK value should be set up by the software prior to receiving the byte when hardware ACK generation is enabled. The interface exits Slave Receiver Mode after receiving a STOP. Note that the interface will switch to Slave Transmitter Mode if SMB0DAT is written while an active Slave Receiver. Figure 21.7 shows a typical slave write sequence. Two received data bytes are shown, though any number of bytes may be received. Notice that the `data byte transferred' interrupts occur at different places in the sequence, depending on whether hardware ACK generation is enabled. The interrupt occurs before the ACK with hardware ACK generation disabled, and after the ACK when hardware ACK generation is enabled. Interrupts with Hardware ACK Enabled (EHACK = 1) S SLA W A Data Byte A Data Byte A P Interrupts with Hardware ACK Disabled (EHACK = 0) Received by SMBus Interface Transmitted by SMBus Interface S = START P = STOP A = ACK W = WRITE SLA = Slave Address Figure 21.7. Typical Slave Write Sequence 160 Rev. 0.2 C8051F336/7/8/9 21.5.4. Read Sequence (Slave) During a read sequence, an SMBus master reads data from a slave device. The slave in this transfer will be a receiver during the address byte, and a transmitter during all data bytes. When slave events are enabled (INH = 0), the interface enters Slave Receiver Mode (to receive the slave address) when a START followed by a slave address and direction bit (READ in this case) is received. If hardware ACK generation is disabled, upon entering Slave Receiver Mode, an interrupt is generated and the ACKRQ bit is set. The software must respond to the received slave address with an ACK, or ignore the received slave address with a NACK. If hardware ACK generation is enabled, the hardware will apply the ACK for a slave address which matches the criteria set up by SMB0ADR and SMB0ADM. The interrupt will occur after the ACK cycle. If the received slave address is ignored (by software or hardware), slave interrupts will be inhibited until the next START is detected. If the received slave address is acknowledged, zero or more data bytes are transmitted. If the received slave address is acknowledged, data should be written to SMB0DAT to be transmitted. The interface enters Slave Transmitter Mode, and transmits one or more bytes of data. After each byte is transmitted, the master sends an acknowledge bit; if the acknowledge bit is an ACK, SMB0DAT should be written with the next data byte. If the acknowledge bit is a NACK, SMB0DAT should not be written to before SI is cleared (Note: an error condition may be generated if SMB0DAT is written following a received NACK while in Slave Transmitter Mode). The interface exits Slave Transmitter Mode after receiving a STOP. Note that the interface will switch to Slave Receiver Mode if SMB0DAT is not written following a Slave Transmitter interrupt. Figure 21.8 shows a typical slave read sequence. Two transmitted data bytes are shown, though any number of bytes may be transmitted. Notice that all of the `data byte transferred' interrupts occur after the ACK cycle in this mode, regardless of whether hardware ACK generation is enabled. Interrupts with Hardware ACK Enabled (EHACK = 1) S SLA R A Data Byte A Data Byte N P Interrupts with Hardware ACK Disabled (EHACK = 0) Received by SMBus Interface Transmitted by SMBus Interface S = START P = STOP N = NACK R = READ SLA = Slave Address Figure 21.8. Typical Slave Read Sequence 21.6. SMBus Status Decoding The current SMBus status can be easily decoded using the SMB0CN register. The appropriate actions to take in response to an SMBus event depend on whether hardware slave address recognition and ACK generation is enabled or disabled. Table 21.5 describes the typical actions when hardware slave address recognition and ACK generation is disabled. Table 21.6 describes the typical actions when hardware slave address recognition and ACK generation is enabled. In the tables, STATUS VECTOR refers to the four upper bits of SMB0CN: MASTER, TXMODE, STA, and STO. The shown response options are only the typ- Rev. 0.2 161 C8051F336/7/8/9 ical responses; application-specific procedures are allowed as long as they conform to the SMBus specification. Highlighted responses are allowed by hardware but do not conform to the SMBus specification. Table 21.5. SMBus Status Decoding With Hardware ACK Generation Disabled (EHACK = 0) Values Read Mode ARBLOST ACKRQ Status Vector Current SMbus State Typical Response Options STO STA Values to Write ACK 1 0 0 1 0 1 0 Next Status Vector Expected 1100 1110 1100 1110 1000 1000 1110 1110 1110 1100 1100 ACK 1110 0 0 0X 0 A master START was generated. Load slave address + R/W into SMB0DAT. 0 1 0 0 0 0X 0X 1X 0X 1X 1X 0X 0X 0 1 1 0 0 0 Master Transmitter A master data or address byte Set STA to restart transfer. 0 was transmitted; NACK Abort transfer. received. Load next data byte into SMB0DAT. 1100 0 0 End transfer with STOP. A master data or address byte End transfer with STOP and start 1 another transfer. 1 was transmitted; ACK received. Send repeated START. 1 Switch to Master Receiver Mode (clear SI without writing new data 0 to SMB0DAT). Acknowledge received byte; Read SMB0DAT. 0 Send NACK to indicate last byte, 0 and send STOP. Send NACK to indicate last byte, and send STOP followed by 1 START. 1000 1 0X A master data byte was received; ACK requested. Send ACK followed by repeated START. 1 Master Receiver Send NACK to indicate last byte, 1 and send repeated START. Send ACK and switch to Master Transmitter Mode (write to SMB0DAT before clearing SI). Send NACK and switch to Master Transmitter Mode (write to SMB0DAT before clearing SI). 0 0 0 162 Rev. 0.2 C8051F336/7/8/9 Table 21.5. SMBus Status Decoding With Hardware ACK Generation Disabled (EHACK = 0) (Continued) Values Read Mode ARBLOST ACKRQ Status Vector Current SMbus State Typical Response Options STO STA Values to Write ACK 1 1 0 1 1 0 0 0 1 0 0 0 Next Status Vector Expected 0001 0100 0001 0000 0100 0000 0100 1110 0000 1110 1110 1110 163 ACK 0 Slave Transmitter 0100 0 0 0101 0 0 0 1 A slave byte was transmitted; No action required (expecting NACK received. STOP condition). A slave byte was transmitted; Load SMB0DAT with next data ACK received. byte to transmit. A Slave byte was transmitted; No action required (expecting error detected. Master to end transfer). 0 0 0 0 0 0X 0X 0X 0X 0 0 0 0 0 0 0 1X An illegal STOP or bus error Clear STO. 0 X X was detected while a Slave Transmission was in progress. If Write, Acknowledge received address 1 0X A slave address + R/W was received; ACK requested. If Read, Load SMB0DAT with 0 data byte; ACK received address NACK received address. 0 0 If Write, Acknowledge received address 0010 Slave Receiver 1 If Read, Load SMB0DAT with Lost arbitration as master; 0 1 X slave address + R/W received; data byte; ACK received address ACK requested. NACK received address. 0 Reschedule failed transfer; NACK received address. 1 0 0 0 0 0 1 0 1 0 1 0 0001 1 A STOP was detected while 0 X addressed as a Slave Transmitter or Slave Receiver. 1X Clear STO. 0X 0 0 0 Lost arbitration while attempt- No action required (transfer complete/aborted). ing a STOP. A slave byte was received; ACK requested. Acknowledge received byte; Read SMB0DAT. NACK received byte. 0000 Bus Error Condition 1 0X 0010 0001 0000 0 0 1 1X 1X 1X Lost arbitration while attempt- Abort failed transfer. ing a repeated START. Reschedule failed transfer. Lost arbitration due to a detected STOP. Abort failed transfer. Reschedule failed transfer. 0X 0X 0X 0X 0 0 Lost arbitration while transmit- Abort failed transfer. ting a data byte as master. Reschedule failed transfer. Rev. 0.2 C8051F336/7/8/9 Table 21.6. SMBus Status Decoding With Hardware ACK Generation Enabled (EHACK = 1) Values Read Mode ARBLOST ACKRQ Status Vector Current SMbus State Typical Response Options STO STA Values to Write ACK 1 1 0 0 0 0 0 Next Status Vector Expected 1100 1110 1100 1110 1000 1000 1000 1110 1100 1110 1110 1100 ACK 1110 0 0 0X 0 A master START was generated. Load slave address + R/W into SMB0DAT. 0 1 0 0 0 0X 0X 1X 0X 1X 1X 0X 0 Master Transmitter A master data or address byte Set STA to restart transfer. 0 was transmitted; NACK Abort transfer. received. Load next data byte into SMB0DAT. End transfer with STOP. 1100 0 0 End transfer with STOP and start A master data or address byte 1 another transfer. 1 was transmitted; ACK Send repeated START. 1 received. Switch to Master Receiver Mode (clear SI without writing new data 0 to SMB0DAT). Set ACK for initial data byte. Set ACK for next data byte; Read SMB0DAT. Set NACK to indicate next data byte as the last data byte; Read SMB0DAT. Initiate repeated START. 0 0 1 0 0 0 0 Master Receiver 0 1 A master data byte was received; ACK sent. 1000 Switch to Master Transmitter Mode (write to SMB0DAT before 0 clearing SI). Read SMB0DAT; send STOP. A master data byte was 0 received; NACK sent (last byte). Read SMB0DAT; Send STOP followed by START. Initiate repeated START. 0 1 1 0X 1 1 0 0 0 Switch to Master Transmitter Mode (write to SMB0DAT before 0 clearing SI). 0X 164 Rev. 0.2 C8051F336/7/8/9 Table 21.6. SMBus Status Decoding With Hardware ACK Generation Enabled (EHACK = 1) (Continued) Values Read Mode ARBLOST ACKRQ Status Vector Current SMbus State Typical Response Options STO STA Values to Write ACK 1 1 0 1 0 Next Status Vector Expected 0001 0100 0001 0000 0100 0000 0100 1110 0000 0000 1110 1110 1110 165 ACK 0 Slave Transmitter 0100 0 0 0101 0 0 0 1 A slave byte was transmitted; No action required (expecting NACK received. STOP condition). A slave byte was transmitted; Load SMB0DAT with next data ACK received. byte to transmit. A Slave byte was transmitted; No action required (expecting error detected. Master to end transfer). 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 1 0X 0X 0X 0X 0 1X An illegal STOP or bus error Clear STO. 0 X X was detected while a Slave Transmission was in progress. A slave address + R/W was 0X received; ACK sent. If Write, Set ACK for first data byte. If Read, Load SMB0DAT with data byte If Write, Set ACK for first data byte. 0 0X 0 0010 Slave Receiver 0 Lost arbitration as master; 1 X slave address + R/W received; If Read, Load SMB0DAT with ACK sent. data byte Reschedule failed transfer A STOP was detected while 0 X addressed as a Slave Transmitter or Slave Receiver. 1X 0X 0X 0X 0 0 0 0 0001 0 Clear STO. Lost arbitration while attempt- No action required (transfer complete/aborted). ing a STOP. Set ACK for next data byte; Read SMB0DAT. Set NACK for next data byte; Read SMB0DAT. 0000 0 0 X A slave byte was received. Bus Error Condition 0010 0001 0000 0 0 0 1X 1X 1X Lost arbitration while attempt- Abort failed transfer. ing a repeated START. Reschedule failed transfer. Lost arbitration due to a detected STOP. Abort failed transfer. Reschedule failed transfer. 0X 0X 0X 0X 0X 0X Lost arbitration while transmit- Abort failed transfer. ting a data byte as master. Reschedule failed transfer. Rev. 0.2 C8051F336/7/8/9 22. UART0 UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART. Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details in Section "22.1. Enhanced Baud Rate Generation" on page 167). Received data buffering allows UART0 to start reception of a second incoming data byte before software has finished reading the previous data byte. UART0 has two associated SFRs: Serial Control Register 0 (SCON0) and Serial Data Buffer 0 (SBUF0). The single SBUF0 location provides access to both transmit and receive registers. Writes to SBUF0 always access the Transmit register. Reads of SBUF0 always access the buffered Receive register; it is not possible to read data from the Transmit register. With UART0 interrupts enabled, an interrupt is generated each time a transmit is completed (TI0 is set in SCON0), or a data byte has been received (RI0 is set in SCON0). The UART0 interrupt flags are not cleared by hardware when the CPU vectors to the interrupt service routine. They must be cleared manually by software, allowing software to determine the cause of the UART0 interrupt (transmit complete or receive complete). SFR Bus Write to SBUF TB8 SET D CLR Q SBUF (TX Shift) TX Crossbar Zero Detector Stop Bit Start Tx Clock Shift Data Tx Control Tx IRQ Send SCON SMODE MCE REN TB8 RB8 TI RI UART Baud Rate Generator TI Serial Port Interrupt RI Port I/O Rx IRQ Rx Clock Rx Control Start Shift 0x1FF RB8 Load SBUF Input Shift Register (9 bits) Load SBUF SBUF (RX Latch) Read SBUF SFR Bus RX Crossbar Figure 22.1. UART0 Block Diagram 166 Rev. 0.2 C8051F336/7/8/9 22.1. Enhanced Baud Rate Generation The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer in Figure 22.2), which is not useraccessible. Both TX and RX Timer overflows are divided by two to generate the TX and RX baud rates. The RX Timer runs when Timer 1 is enabled, and uses the same reload value (TH1). However, an RX Timer reload is forced when a START condition is detected on the RX pin. This allows a receive to begin any time a START is detected, independent of the TX Timer state. Timer 1 TL1 Overflow UART 2 TX Clock TH1 Start Detected RX Timer Overflow 2 RX Clock Figure 22.2. UART0 Baud Rate Logic Timer 1 should be configured for Mode 2, 8-bit auto-reload (see Section "24.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload" on page 191). The Timer 1 reload value should be set so that overflows will occur at two times the desired UART baud rate frequency. Note that Timer 1 may be clocked by one of six sources: SYSCLK, SYSCLK / 4, SYSCLK / 12, SYSCLK / 48, the external oscillator clock / 8, or an external input T1. For any given Timer 1 clock source, the UART0 baud rate is determined by Equation 22.1-A and Equation 22.1-B. A) B) 1 UartBaudRate = -- x T1_Overflow_Rate 2 T1 CLK T1_Overflow_Rate = ------------------------256 - TH1 Equation 22.1. UART0 Baud Rate Where T1CLK is the frequency of the clock supplied to Timer 1, and T1H is the high byte of Timer 1 (reload value). Timer 1 clock frequency is selected as described in Section "24. Timers" on page 187. A quick reference for typical baud rates and system clock frequencies is given in Table 22.1 through Table 22.2. Note that the internal oscillator may still generate the system clock when the external oscillator is driving Timer 1. Rev. 0.2 167 C8051F336/7/8/9 22.2. Operational Modes UART0 provides standard asynchronous, full duplex communication. The UART mode (8-bit or 9-bit) is selected by the S0MODE bit (SCON0.7). Typical UART connection options are shown in Figure 22.3. RS-232 RS-232 LEVEL XLTR TX RX C8051Fxxx OR TX TX MCU RX RX C8051Fxxx Figure 22.3. UART Interconnect Diagram 22.2.1. 8-Bit UART 8-Bit UART mode uses a total of 10 bits per data byte: one start bit, eight data bits (LSB first), and one stop bit. Data are transmitted LSB first from the TX0 pin and received at the RX0 pin. On receive, the eight data bits are stored in SBUF0 and the stop bit goes into RB80 (SCON0.2). Data transmission begins when software writes a data byte to the SBUF0 register. The TI0 Transmit Interrupt Flag (SCON0.1) is set at the end of the transmission (the beginning of the stop-bit time). Data reception can begin any time after the REN0 Receive Enable bit (SCON0.4) is set to logic 1. After the stop bit is received, the data byte will be loaded into the SBUF0 receive register if the following conditions are met: RI0 must be logic 0, and if MCE0 is logic 1, the stop bit must be logic 1. In the event of a receive data overrun, the first received 8 bits are latched into the SBUF0 receive register and the following overrun data bits are lost. If these conditions are met, the eight bits of data is stored in SBUF0, the stop bit is stored in RB80 and the RI0 flag is set. If these conditions are not met, SBUF0 and RB80 will not be loaded and the RI0 flag will not be set. An interrupt will occur if enabled when either TI0 or RI0 is set. MARK SPACE BIT TIMES START BIT D0 D1 D2 D3 D4 D5 D6 D7 STOP BIT BIT SAMPLING Figure 22.4. 8-Bit UART Timing Diagram 168 Rev. 0.2 C8051F336/7/8/9 22.2.2. 9-Bit UART 9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programmable ninth data bit, and a stop bit. The state of the ninth transmit data bit is determined by the value in TB80 (SCON0.3), which is assigned by user software. It can be assigned the value of the parity flag (bit P in register PSW) for error detection, or used in multiprocessor communications. On receive, the ninth data bit goes into RB80 (SCON0.2) and the stop bit is ignored. Data transmission begins when an instruction writes a data byte to the SBUF0 register. The TI0 Transmit Interrupt Flag (SCON0.1) is set at the end of the transmission (the beginning of the stop-bit time). Data reception can begin any time after the REN0 Receive Enable bit (SCON0.4) is set to `1'. After the stop bit is received, the data byte will be loaded into the SBUF0 receive register if the following conditions are met: (1) RI0 must be logic 0, and (2) if MCE0 is logic 1, the 9th bit must be logic 1 (when MCE0 is logic 0, the state of the ninth data bit is unimportant). If these conditions are met, the eight bits of data are stored in SBUF0, the ninth bit is stored in RB80, and the RI0 flag is set to `1'. If the above conditions are not met, SBUF0 and RB80 will not be loaded and the RI0 flag will not be set to `1'. A UART0 interrupt will occur if enabled when either TI0 or RI0 is set to `1'. MARK SPACE BIT TIMES START BIT D0 D1 D2 D3 D4 D5 D6 D7 D8 STOP BIT BIT SAMPLING Figure 22.5. 9-Bit UART Timing Diagram 22.3. Multiprocessor Communications 9-Bit UART mode supports multiprocessor communication between a master processor and one or more slave processors by special use of the ninth data bit. When a master processor wants to transmit to one or more slaves, it first sends an address byte to select the target(s). An address byte differs from a data byte in that its ninth bit is logic 1; in a data byte, the ninth bit is always set to logic 0. Setting the MCE0 bit (SCON0.5) of a slave processor configures its UART such that when a stop bit is received, the UART will generate an interrupt only if the ninth bit is logic 1 (RB80 = 1) signifying an address byte has been received. In the UART interrupt handler, software will compare the received address with the slave's own assigned 8-bit address. If the addresses match, the slave will clear its MCE0 bit to enable interrupts on the reception of the following data byte(s). Slaves that weren't addressed leave their MCE0 bits set and do not generate interrupts on the reception of the following data bytes, thereby ignoring the data. Once the entire message is received, the addressed slave resets its MCE0 bit to ignore all transmissions until it receives the next address byte. Multiple addresses can be assigned to a single slave and/or a single address can be assigned to multiple slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. The master processor can be configured to receive all transmissions or a protocol can be implemented such that the master/slave role is temporarily reversed to enable half-duplex transmission between the original master and slave(s). Rev. 0.2 169 C8051F336/7/8/9 Master Device RX TX Slave Device RX TX Slave Device RX TX Slave Device V+ RX TX Figure 22.6. UART Multi-Processor Mode Interconnect Diagram 170 Rev. 0.2 C8051F336/7/8/9 SFR Definition 22.1. SCON0: Serial Port 0 Control Bit Name Type Reset 7 S0MODE R/W 0 R 1 6 5 MCE0 R/W 0 4 REN0 R/W 0 3 TB80 R/W 0 2 RB80 R/W 0 1 TI0 R/W 0 0 RI0 R/W 0 SFR Address = 0x98; Bit-Addressable Bit Name 7 Function S0MODE Serial Port 0 Operation Mode. Selects the UART0 Operation Mode. 0: 8-bit UART with Variable Baud Rate. 1: 9-bit UART with Variable Baud Rate. UNUSED Unused. Read = 1b, Write = Don't Care. MCE0 Multiprocessor Communication Enable. The function of this bit is dependent on the Serial Port 0 Operation Mode: Mode 0: Checks for valid stop bit. 0: Logic level of stop bit is ignored. 1: RI0 will only be activated if stop bit is logic level 1. Mode 1: Multiprocessor Communications Enable. 0: Logic level of ninth bit is ignored. 1: RI0 is set and an interrupt is generated only when the ninth bit is logic 1. 6 5 4 REN0 Receive Enable. 0: UART0 reception disabled. 1: UART0 reception enabled. 3 TB80 Ninth Transmission Bit. The logic level of this bit will be sent as the ninth transmission bit in 9-bit UART Mode (Mode 1). Unused in 8-bit mode (Mode 0). 2 RB80 Ninth Receive Bit. RB80 is assigned the value of the STOP bit in Mode 0; it is assigned the value of the 9th data bit in Mode 1. 1 TI0 Transmit Interrupt Flag. Set by hardware when a byte of data has been transmitted by UART0 (after the 8th bit in 8-bit UART Mode, or at the beginning of the STOP bit in 9-bit UART Mode). When the UART0 interrupt is enabled, setting this bit causes the CPU to vector to the UART0 interrupt service routine. This bit must be cleared manually by software. 0 RI0 Receive Interrupt Flag. Set to `1' by hardware when a byte of data has been received by UART0 (set at the STOP bit sampling time). When the UART0 interrupt is enabled, setting this bit to `1' causes the CPU to vector to the UART0 interrupt service routine. This bit must be cleared manually by software. Rev. 0.2 171 C8051F336/7/8/9 SFR Definition 22.2. SBUF0: Serial (UART0) Port Data Buffer Bit Name Type Reset 0 0 0 0 7 6 5 4 3 2 1 0 SBUF0[7:0] R/W 0 0 0 0 SFR Address = 0x99 Bit Name 7:0 Function SBUF0[7:0] Serial Data Buffer Bits 7-0 (MSB-LSB) This SFR accesses two registers; a transmit shift register and a receive latch register. When data is written to SBUF0, it goes to the transmit shift register and is held for serial transmission. Writing a byte to SBUF0 initiates the transmission. A read of SBUF0 returns the contents of the receive latch. 172 Rev. 0.2 C8051F336/7/8/9 Table 22.1. Timer Settings for Standard Baud Rates Using The Internal 24.5 MHz Oscillator Target Baud Rate (bps) 230400 115200 57600 28800 14400 9600 2400 1200 Baud Rate % Error -0.32% -0.32% 0.15% -0.32% 0.15% -0.32% -0.32% 0.15% Frequency: 24.5 MHz Oscilla- Timer Clock SCA1-SCA0 tor Divide Source (pre-scale Factor select)1 106 SYSCLK XX2 212 SYSCLK XX 426 SYSCLK XX 848 SYSCLK/4 01 1704 SYSCLK/12 00 2544 SYSCLK/12 00 10176 SYSCLK/48 10 20448 SYSCLK/48 10 T1M1 Timer 1 Reload Value (hex) 0xCB 0x96 0x2B 0x96 0xB9 0x96 0x96 0x2B 1 1 1 0 0 0 0 0 Notes: 1. SCA1-SCA0 and T1M bit definitions can be found in Section 24.1. 2. X = Don't care. SYSCLK from Internal Osc. Table 22.2. Timer Settings for Standard Baud Rates Using an External 22.1184 MHz Oscillator Target Baud Rate (bps) 230400 115200 57600 28800 14400 9600 2400 1200 230400 115200 57600 28800 14400 9600 Baud Rate % Error 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% Frequency: 22.1184 MHz Oscilla- Timer Clock SCA1-SCA0 tor Divide Source (pre-scale Factor select)1 96 SYSCLK XX2 192 SYSCLK XX 384 SYSCLK XX 768 SYSCLK / 12 00 1536 SYSCLK / 12 00 2304 SYSCLK / 12 00 9216 SYSCLK / 48 10 18432 SYSCLK / 48 10 96 EXTCLK / 8 11 192 EXTCLK / 8 11 384 EXTCLK / 8 11 768 EXTCLK / 8 11 1536 EXTCLK / 8 11 2304 EXTCLK / 8 11 T1M1 Timer 1 Reload Value (hex) 0xD0 0xA0 0x40 0xE0 0xC0 0xA0 0xA0 0x40 0xFA 0xF4 0xE8 0xD0 0xA0 0x70 1 1 1 0 0 0 0 0 0 0 0 0 0 0 Notes: 1. SCA1-SCA0 and T1M bit definitions can be found in Section 24.1. 2. X = Don't care. SYSCLK from Internal Osc. SYSCLK from External Osc. Rev. 0.2 173 C8051F336/7/8/9 23. Enhanced Serial Peripheral Interface (SPI0) The Enhanced Serial Peripheral Interface (SPI0) provides access to a flexible, full-duplex synchronous serial bus. SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports multiple masters and slaves on a single SPI bus. The slave-select (NSS) signal can be configured as an input to select SPI0 in slave mode, or to disable Master Mode operation in a multi-master environment, avoiding contention on the SPI bus when more than one master attempts simultaneous data transfers. NSS can also be configured as a chip-select output in master mode, or disabled for 3-wire operation. Additional general purpose port I/O pins can be used to select multiple slave devices in master mode. SFR Bus SPI0CKR SCR7 SCR6 SCR5 SCR4 SCR3 SCR2 SCR1 SCR0 SPI0CFG SPIBSY MSTEN CKPHA CKPOL SLVSEL NSSIN SRMT RXBMT SPI0CN SPIF WCOL MODF RXOVRN NSSMD1 NSSMD0 TXBMT SPIEN SYSCLK Clock Divide Logic SPI CONTROL LOGIC Data Path Control Pin Interface Control SPI IRQ Tx Data MOSI SPI0DAT Transmit Data Buffer Pin Control Logic SCK Shift Register 76543210 Rx Data MISO C R O S S B A R Port I/O Receive Data Buffer NSS Write SPI0DAT Read SPI0DAT SFR Bus Figure 23.1. SPI Block Diagram 174 Rev. 0.2 C8051F336/7/8/9 23.1. Signal Descriptions The four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below. 23.1.1. Master Out, Slave In (MOSI) The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave devices. It is used to serially transfer data from the master to the slave. This signal is an output when SPI0 is operating as a master and an input when SPI0 is operating as a slave. Data is transferred most-significant bit first. When configured as a master, MOSI is driven by the MSB of the shift register in both 3- and 4-wire mode. 23.1.2. Master In, Slave Out (MISO) The master-in, slave-out (MISO) signal is an output from a slave device and an input to the master device. It is used to serially transfer data from the slave to the master. This signal is an input when SPI0 is operating as a master and an output when SPI0 is operating as a slave. Data is transferred most-significant bit first. The MISO pin is placed in a high-impedance state when the SPI module is disabled and when the SPI operates in 4-wire mode as a slave that is not selected. When acting as a slave in 3-wire mode, MISO is always driven by the MSB of the shift register. 23.1.3. Serial Clock (SCK) The serial clock (SCK) signal is an output from the master device and an input to slave devices. It is used to synchronize the transfer of data between the master and slave on the MOSI and MISO lines. SPI0 generates this signal when operating as a master. The SCK signal is ignored by a SPI slave when the slave is not selected (NSS = 1) in 4-wire slave mode. 23.1.4. Slave Select (NSS) The function of the slave-select (NSS) signal is dependent on the setting of the NSSMD1 and NSSMD0 bits in the SPI0CN register. There are three possible modes that can be selected with these bits: 1. NSSMD[1:0] = 00: 3-Wire Master or 3-Wire Slave Mode: SPI0 operates in 3-wire mode, and NSS is disabled. When operating as a slave device, SPI0 is always selected in 3-wire mode. Since no select signal is present, SPI0 must be the only slave on the bus in 3-wire mode. This is intended for point-to-point communication between a master and one slave. 2. NSSMD[1:0] = 01: 4-Wire Slave or Multi-Master Mode: SPI0 operates in 4-wire mode, and NSS is enabled as an input. When operating as a slave, NSS selects the SPI0 device. When operating as a master, a 1-to-0 transition of the NSS signal disables the master function of SPI0 so that multiple master devices can be used on the same SPI bus. 3. NSSMD[1:0] = 1x: 4-Wire Master Mode: SPI0 operates in 4-wire mode, and NSS is enabled as an output. The setting of NSSMD0 determines what logic level the NSS pin will output. This configuration should only be used when operating SPI0 as a master device. See Figure 23.2, Figure 23.3, and Figure 23.4 for typical connection diagrams of the various operational modes. Note that the setting of NSSMD bits affects the pinout of the device. When in 3-wire master or 3-wire slave mode, the NSS pin will not be mapped by the crossbar. In all other modes, the NSS signal will be mapped to a pin on the device. See Section "20. Port Input/Output" on page 126 for general purpose port I/O and crossbar information. Rev. 0.2 175 C8051F336/7/8/9 23.2. SPI0 Master Mode Operation A SPI master device initiates all data transfers on a SPI bus. SPI0 is placed in master mode by setting the Master Enable flag (MSTEN, SPI0CN.6). Writing a byte of data to the SPI0 data register (SPI0DAT) when in master mode writes to the transmit buffer. If the SPI shift register is empty, the byte in the transmit buffer is moved to the shift register, and a data transfer begins. The SPI0 master immediately shifts out the data serially on the MOSI line while providing the serial clock on SCK. The SPIF (SPI0CN.7) flag is set to logic 1 at the end of the transfer. If interrupts are enabled, an interrupt request is generated when the SPIF flag is set. While the SPI0 master transfers data to a slave on the MOSI line, the addressed SPI slave device simultaneously transfers the contents of its shift register to the SPI master on the MISO line in a full-duplex operation. Therefore, the SPIF flag serves as both a transmit-complete and receive-data-ready flag. The data byte received from the slave is transferred MSB-first into the master's shift register. When a byte is fully shifted into the register, it is moved to the receive buffer where it can be read by the processor by reading SPI0DAT. When configured as a master, SPI0 can operate in one of three different modes: multi-master mode, 3-wire single-master mode, and 4-wire single-master mode. The default, multi-master mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 1. In this mode, NSS is an input to the device, and is used to disable the master SPI0 when another master is accessing the bus. When NSS is pulled low in this mode, MSTEN (SPI0CN.6) and SPIEN (SPI0CN.0) are set to 0 to disable the SPI master device, and a Mode Fault is generated (MODF, SPI0CN.5 = 1). Mode Fault will generate an interrupt if enabled. SPI0 must be manually re-enabled in software under these circumstances. In multi-master systems, devices will typically default to being slave devices while they are not acting as the system master device. In multi-master mode, slave devices can be addressed individually (if needed) using general-purpose I/O pins. Figure 23.2 shows a connection diagram between two master devices in multiple-master mode. 3-wire single-master mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 0. In this mode, NSS is not used, and is not mapped to an external port pin through the crossbar. Any slave devices that must be addressed in this mode should be selected using general-purpose I/O pins. Figure 23.3 shows a connection diagram between a master device in 3-wire master mode and a slave device. 4-wire single-master mode is active when NSSMD1 (SPI0CN.3) = 1. In this mode, NSS is configured as an output pin, and can be used as a slave-select signal for a single SPI device. In this mode, the output value of NSS is controlled (in software) with the bit NSSMD0 (SPI0CN.2). Additional slave devices can be addressed using general-purpose I/O pins. Figure 23.4 shows a connection diagram for a master device in 4-wire master mode and two slave devices. 176 Rev. 0.2 C8051F336/7/8/9 NSS GPIO MISO MOSI SCK NSS Master Device 1 MISO MOSI SCK GPIO Master Device 2 Figure 23.2. Multiple-Master Mode Connection Diagram Master Device MISO MOSI SCK MISO MOSI SCK Slave Device Figure 23.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram Master Device GPIO MISO MOSI SCK NSS MISO MOSI SCK NSS Slave Device MISO MOSI SCK NSS Slave Device Figure 23.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram Rev. 0.2 177 C8051F336/7/8/9 23.3. SPI0 Slave Mode Operation When SPI0 is enabled and not configured as a master, it will operate as a SPI slave. As a slave, bytes are shifted in through the MOSI pin and out through the MISO pin by a master device controlling the SCK signal. A bit counter in the SPI0 logic counts SCK edges. When 8 bits have been shifted through the shift register, the SPIF flag is set to logic 1, and the byte is copied into the receive buffer. Data is read from the receive buffer by reading SPI0DAT. A slave device cannot initiate transfers. Data to be transferred to the master device is pre-loaded into the shift register by writing to SPI0DAT. Writes to SPI0DAT are doublebuffered, and are placed in the transmit buffer first. If the shift register is empty, the contents of the transmit buffer will immediately be transferred into the shift register. When the shift register already contains data, the SPI will load the shift register with the transmit buffer's contents after the last SCK edge of the next (or current) SPI transfer. When configured as a slave, SPI0 can be configured for 4-wire or 3-wire operation. The default, 4-wire slave mode, is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 1. In 4-wire mode, the NSS signal is routed to a port pin and configured as a digital input. SPI0 is enabled when NSS is logic 0, and disabled when NSS is logic 1. The bit counter is reset on a falling edge of NSS. Note that the NSS signal must be driven low at least 2 system clocks before the first active edge of SCK for each byte transfer. Figure 23.4 shows a connection diagram between two slave devices in 4-wire slave mode and a master device. 3-wire slave mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 0. NSS is not used in this mode, and is not mapped to an external port pin through the crossbar. Since there is no way of uniquely addressing the device in 3-wire slave mode, SPI0 must be the only slave device present on the bus. It is important to note that in 3-wire slave mode there is no external means of resetting the bit counter that determines when a full byte has been received. The bit counter can only be reset by disabling and reenabling SPI0 with the SPIEN bit. Figure 23.3 shows a connection diagram between a slave device in 3wire slave mode and a master device. 23.4. SPI0 Interrupt Sources When SPI0 interrupts are enabled, the following four flags will generate an interrupt when they are set to logic 1: All of the following bits must be cleared by software. 1. The SPI Interrupt Flag, SPIF (SPI0CN.7) is set to logic 1 at the end of each byte transfer. This flag can occur in all SPI0 modes. 2. The Write Collision Flag, WCOL (SPI0CN.6) is set to logic 1 if a write to SPI0DAT is attempted when the transmit buffer has not been emptied to the SPI shift register. When this occurs, the write to SPI0DAT will be ignored, and the transmit buffer will not be written.This flag can occur in all SPI0 modes. 3. The Mode Fault Flag MODF (SPI0CN.5) is set to logic 1 when SPI0 is configured as a master, and for multi-master mode and the NSS pin is pulled low. When a Mode Fault occurs, the MSTEN and SPIEN bits in SPI0CN are set to logic 0 to disable SPI0 and allow another master device to access the bus. 4. The Receive Overrun Flag RXOVRN (SPI0CN.4) is set to logic 1 when configured as a slave, and a transfer is completed and the receive buffer still holds an unread byte from a previous transfer. The new byte is not transferred to the receive buffer, allowing the previously received data byte to be read. The data byte which caused the overrun is lost. 178 Rev. 0.2 C8051F336/7/8/9 23.5. Serial Clock Phase and Polarity Four combinations of serial clock phase and polarity can be selected using the clock control bits in the SPI0 Configuration Register (SPI0CFG). The CKPHA bit (SPI0CFG.5) selects one of two clock phases (edge used to latch the data). The CKPOL bit (SPI0CFG.4) selects between an active-high or active-low clock. Both master and slave devices must be configured to use the same clock phase and polarity. SPI0 should be disabled (by clearing the SPIEN bit, SPI0CN.0) when changing the clock phase or polarity. The clock and data line relationships for master mode are shown in Figure 23.5. For slave mode, the clock and data relationships are shown in Figure 23.6 and Figure 23.7. Note that CKPHA must be set to `0' on both the master and slave SPI when communicating between two of the following devices: C8051F04x, C8051F06x, C8051F12x, C8051F31x, C8051F32x, and C8051F33x The SPI0 Clock Rate Register (SPI0CKR) as shown in SFR Definition 23.3 controls the master mode serial clock frequency. This register is ignored when operating in slave mode. When the SPI is configured as a master, the maximum data transfer rate (bits/sec) is one-half the system clock frequency or 12.5 MHz, whichever is slower. When the SPI is configured as a slave, the maximum data transfer rate (bits/sec) for full-duplex operation is 1/10 the system clock frequency, provided that the master issues SCK, NSS (in 4wire slave mode), and the serial input data synchronously with the slave's system clock. If the master issues SCK, NSS, and the serial input data asynchronously, the maximum data transfer rate (bits/sec) must be less than 1/10 the system clock frequency. In the special case where the master only wants to transmit data to the slave and does not need to receive data from the slave (i.e. half-duplex operation), the SPI slave can receive data at a maximum data transfer rate (bits/sec) of 1/4 the system clock frequency. This is provided that the master issues SCK, NSS, and the serial input data synchronously with the slave's system clock. SCK (CKPOL=0, CKPHA=0) SCK (CKPOL=0, CKPHA=1) SCK (CKPOL=1, CKPHA=0) SCK (CKPOL=1, CKPHA=1) MISO/MOSI MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 NSS (Must Remain High in Multi-Master Mode) Figure 23.5. Master Mode Data/Clock Timing Rev. 0.2 179 C8051F336/7/8/9 SCK (CKPOL=0, CKPHA=0) SCK (CKPOL=1, CKPHA=0) MOSI MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MISO MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 NSS (4-Wire Mode) Figure 23.6. Slave Mode Data/Clock Timing (CKPHA = 0) SCK (CKPOL=0, CKPHA=1) SCK (CKPOL=1, CKPHA=1) MOSI MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MISO MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 NSS (4-Wire Mode) Figure 23.7. Slave Mode Data/Clock Timing (CKPHA = 1) 23.6. SPI Special Function Registers SPI0 is accessed and controlled through four special function registers in the system controller: SPI0CN Control Register, SPI0DAT Data Register, SPI0CFG Configuration Register, and SPI0CKR Clock Rate Register. The four special function registers related to the operation of the SPI0 Bus are described in the following figures. 180 Rev. 0.2 C8051F336/7/8/9 SFR Definition 23.1. SPI0CFG: SPI0 Configuration Bit Name Type Reset 7 SPIBSY R 0 6 MSTEN R/W 0 5 CKPHA R/W 0 4 CKPOL R/W 0 3 SLVSEL R 0 2 NSSIN R 1 1 SRMT R 1 0 RXBMT R 1 SFR Address = 0xA1 Bit Name 7 6 SPIBSY MSTEN SPI Busy. Function This bit is set to logic 1 when a SPI transfer is in progress (master or slave mode). Master Mode Enable. 0: Disable master mode. Operate in slave mode. 1: Enable master mode. Operate as a master. 5 CKPHA SPI0 Clock Phase. 0: Data centered on first edge of SCK period.* 1: Data centered on second edge of SCK period.* 4 CKPOL SPI0 Clock Polarity. 0: SCK line low in idle state. 1: SCK line high in idle state. 3 SLVSEL Slave Selected Flag. This bit is set to logic 1 whenever the NSS pin is low indicating SPI0 is the selected slave. It is cleared to logic 0 when NSS is high (slave not selected). This bit does not indicate the instantaneous value at the NSS pin, but rather a de-glitched version of the pin input. 2 NSSIN NSS Instantaneous Pin Input. This bit mimics the instantaneous value that is present on the NSS port pin at the time that the register is read. This input is not de-glitched. 1 SRMT Shift Register Empty (valid in slave mode only). This bit will be set to logic 1 when all data has been transferred in/out of the shift register, and there is no new information available to read from the transmit buffer or write to the receive buffer. It returns to logic 0 when a data byte is transferred to the shift register from the transmit buffer or by a transition on SCK. SRMT = 1 when in Master Mode. 0 RXBMT Receive Buffer Empty (valid in slave mode only). This bit will be set to logic 1 when the receive buffer has been read and contains no new information. If there is new information available in the receive buffer that has not been read, this bit will return to logic 0. RXBMT = 1 when in Master Mode. *Note: In slave mode, data on MOSI is sampled in the center of each data bit. In master mode, data on MISO is sampled one SYSCLK before the end of each data bit, to provide maximum settling time for the slave device. See Table 23.1 for timing parameters. Rev. 0.2 181 C8051F336/7/8/9 SFR Definition 23.2. SPI0CN: SPI0 Control Bit Name Type Reset 7 SPIF R/W 0 6 WCOL R/W 0 5 MODF R/W 0 4 RXOVRN R/W 0 0 3 2 1 TXBMT R 1 1 0 SPIEN R/W 0 NSSMD[1:0] R/W SFR Address = 0xF8; Bit-Addressable Bit Name 7 SPIF SPI0 Interrupt Flag. Function This bit is set to logic 1 by hardware at the end of a data transfer. If interrupts are enabled, setting this bit causes the CPU to vector to the SPI0 interrupt service routine. This bit is not automatically cleared by hardware. It must be cleared by software. 6 WCOL Write Collision Flag. This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) to indicate a write to the SPI0 data register was attempted while a data transfer was in progress. It must be cleared by software. 5 MODF Mode Fault Flag. This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) when a master mode collision is detected (NSS is low, MSTEN = 1, and NSSMD[1:0] = 01). This bit is not automatically cleared by hardware. It must be cleared by software. 4 RXOVRN Receive Overrun Flag (valid in slave mode only). This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) when the receive buffer still holds unread data from a previous transfer and the last bit of the current transfer is shifted into the SPI0 shift register. This bit is not automatically cleared by hardware. It must be cleared by software. 3:2 NSSMD[1:0] Slave Select Mode. Selects between the following NSS operation modes: (See Section 23.2 and Section 23.3). 00: 3-Wire Slave or 3-Wire Master Mode. NSS signal is not routed to a port pin. 01: 4-Wire Slave or Multi-Master Mode (Default). NSS is an input to the device. 1x: 4-Wire Single-Master Mode. NSS signal is mapped as an output from the device and will assume the value of NSSMD0. 1 TXBMT Transmit Buffer Empty. This bit will be set to logic 0 when new data has been written to the transmit buffer. When data in the transmit buffer is transferred to the SPI shift register, this bit will be set to logic 1, indicating that it is safe to write a new byte to the transmit buffer. 0 SPIEN SPI0 Enable. 0: SPI disabled. 1: SPI enabled. 182 Rev. 0.2 C8051F336/7/8/9 SFR Definition 23.3. SPI0CKR: SPI0 Clock Rate Bit Name Type Reset 0 0 0 0 7 6 5 4 SCR[7:0] R/W 0 0 0 0 3 2 1 0 SFR Address = 0xA2 Bit Name 7:0 SCR[7:0] SPI0 Clock Rate. Function These bits determine the frequency of the SCK output when the SPI0 module is configured for master mode operation. The SCK clock frequency is a divided version of the system clock, and is given in the following equation, where SYSCLK is the system clock frequency and SPI0CKR is the 8-bit value held in the SPI0CKR register. SYSCLK f SCK = ---------------------------------------------------------2 x ( SPI0CKR[7:0] + 1 ) for 0 <= SPI0CKR <= 255 Example: If SYSCLK = 2 MHz and SPI0CKR = 0x04, 2000000 f SCK = ------------------------2 x (4 + 1) f SCK = 200kHz SFR Definition 23.4. SPI0DAT: SPI0 Data Bit Name Type Reset 0 0 0 0 7 6 5 4 3 2 1 0 SPI0DAT[7:0] R/W 0 0 0 0 SFR Address = 0xA3 Bit Name 7:0 SPI0DAT[7:0] SPI0 Transmit and Receive Data. Function The SPI0DAT register is used to transmit and receive SPI0 data. Writing data to SPI0DAT places the data into the transmit buffer and initiates a transfer when in Master Mode. A read of SPI0DAT returns the contents of the receive buffer. Rev. 0.2 183 C8051F336/7/8/9 SCK* T T MCKH MCKL T MIS T MIH MISO MOSI * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 23.8. SPI Master Timing (CKPHA = 0) SCK* T T MCKH MCKL T MIS T MIH MISO MOSI * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 23.9. SPI Master Timing (CKPHA = 1) 184 Rev. 0.2 C8051F336/7/8/9 NSS T T T SE CKL SD SCK* T CKH T SIS T SIH MOSI T SEZ T SOH T SDZ MISO * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 23.10. SPI Slave Timing (CKPHA = 0) NSS T T T SE CKL SD SCK* T CKH T SIS T SIH MOSI T T SEZ SOH T SLH T SDZ MISO * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 23.11. SPI Slave Timing (CKPHA = 1) Rev. 0.2 185 C8051F336/7/8/9 Table 23.1. SPI Slave Timing Parameters Parameter * Description Min Max Units Master Mode Timing (See Figure 23.8 and Figure 23.9) TMCKH TMCKL TMIS TMIH SCK High Time SCK Low Time MISO Valid to SCK Shift Edge SCK Shift Edge to MISO Change 1 x TSYSCLK 1 x TSYSCLK 1 x TSYSCLK + 20 0 -- -- -- -- ns ns ns ns Slave Mode Timing* (See Figure 23.10 and Figure 23.11) TSE TSD TSEZ TSDZ TCKH TCKL TSIS TSIH TSOH TSLH NSS Falling to First SCK Edge Last SCK Edge to NSS Rising NSS Falling to MISO Valid NSS Rising to MISO High-Z SCK High Time SCK Low Time MOSI Valid to SCK Sample Edge SCK Sample Edge to MOSI Change SCK Shift Edge to MISO Change Last SCK Edge to MISO Change (CKPHA = 1 ONLY) 2 x TSYSCLK 2 x TSYSCLK -- -- 5 x TSYSCLK 5 x TSYSCLK 2 x TSYSCLK 2 x TSYSCLK -- 6 x TSYSCLK -- -- 4 x TSYSCLK 4 x TSYSCLK -- -- -- -- 4 x TSYSCLK 8 x TSYSCLK ns ns ns ns ns ns ns ns ns ns *Note: TSYSCLK is equal to one period of the device system clock (SYSCLK). 186 Rev. 0.2 C8051F336/7/8/9 24. Timers Each MCU includes four counter/timers: two are 16-bit counter/timers compatible with those found in the standard 8051, and two are 16-bit auto-reload timer for use with the ADC, SMBus, or for general purpose use. These timers can be used to measure time intervals, count external events and generate periodic interrupt requests. Timer 0 and Timer 1 are nearly identical and have four primary modes of operation. Timer 2 and Timer 3 offer 16-bit and split 8-bit timer functionality with auto-reload. Additionally, Timer 3 offers the ability to be clocked from the external oscillator while the device is in Suspend mode, and can be used as a wake-up source. This allows for implementation of a very low-power system, including RTC capability. Timer 0 and Timer 1 Modes: 13-bit counter/timer 16-bit counter/timer 8-bit counter/timer with autoreload Two 8-bit counter/timers (Timer 0 only) Timer 2 Modes: 16-bit timer with auto-reload Timer 3 Modes: 16-bit timer with auto-reload Two 8-bit timers with auto-reload Two 8-bit timers with auto-reload Timers 0 and 1 may be clocked by one of five sources, determined by the Timer Mode Select bits (T1M- T0M) and the Clock Scale bits (SCA1-SCA0). The Clock Scale bits define a pre-scaled clock from which Timer 0 and/or Timer 1 may be clocked (See SFR Definition 24.1 for pre-scaled clock selection). Timer 0/1 may then be configured to use this pre-scaled clock signal or the system clock. Timer 2 and Timer 3 may be clocked by the system clock, the system clock divided by 12, or the external oscillator clock source divided by 8. Timer 0 and Timer 1 may also be operated as counters. When functioning as a counter, a counter/timer register is incremented on each high-to-low transition at the selected input pin (T0 or T1). Events with a frequency of up to one-fourth the system clock frequency can be counted. The input signal need not be periodic, but it should be held at a given level for at least two full system clock cycles to ensure the level is properly sampled. Rev. 0.2 187 C8051F336/7/8/9 SFR Definition 24.1. CKCON: Clock Control Bit Name Type Reset 7 T3MH R/W 0 6 T3ML R/W 0 5 T2MH R/W 0 4 T2ML R/W 0 3 T1M R/W 0 2 T0M R/W 0 0 1 SCA[1:0] R/W 0 0 SFR Address = 0x8E Bit Name 7 T3MH Timer 3 High Byte Clock Select. Function Selects the clock supplied to the Timer 3 high byte (split 8-bit timer mode only). 0: Timer 3 high byte uses the clock defined by the T3XCLK bit in TMR3CN. 1: Timer 3 high byte uses the system clock. 6 T3ML Timer 3 Low Byte Clock Select. Selects the clock supplied to Timer 3. Selects the clock supplied to the lower 8-bit timer in split 8-bit timer mode. 0: Timer 3 low byte uses the clock defined by the T3XCLK bit in TMR3CN. 1: Timer 3 low byte uses the system clock. 5 T2MH Timer 2 High Byte Clock Select. Selects the clock supplied to the Timer 2 high byte (split 8-bit timer mode only). 0: Timer 2 high byte uses the clock defined by the T2XCLK bit in TMR2CN. 1: Timer 2 high byte uses the system clock. 4 T2ML Timer 2 Low Byte Clock Select. Selects the clock supplied to Timer 2. If Timer 2 is configured in split 8-bit timer mode, this bit selects the clock supplied to the lower 8-bit timer. 0: Timer 2 low byte uses the clock defined by the T2XCLK bit in TMR2CN. 1: Timer 2 low byte uses the system clock. 3 T1 Timer 1 Clock Select. Selects the clock source supplied to Timer 1. Ignored when C/T1 is set to '1'. 0: Timer 1 uses the clock defined by the prescale bits SCA[1:0]. 1: Timer 1 uses the system clock. 2 T0 Timer 0 Clock Select. Selects the clock source supplied to Timer 0. Ignored when C/T0 is set to '1'. 0: Counter/Timer 0 uses the clock defined by the prescale bits SCA[1:0]. 1: Counter/Timer 0 uses the system clock. 1:0 SCA[1:0] Timer 0/1 Prescale Bits. These bits control the Timer 0/1 Clock Prescaler: 00: System clock divided by 12 01: System clock divided by 4 10: System clock divided by 48 11: External clock divided by 8 (synchronized with the system clock) 188 Rev. 0.2 C8051F336/7/8/9 24.1. Timer 0 and Timer 1 Each timer is implemented as a 16-bit register accessed as two separate bytes: a low byte (TL0 or TL1) and a high byte (TH0 or TH1). The Counter/Timer Control register (TCON) is used to enable Timer 0 and Timer 1 as well as indicate status. Timer 0 interrupts can be enabled by setting the ET0 bit in the IE register (Section "15.2. Interrupt Register Descriptions" on page 91); Timer 1 interrupts can be enabled by setting the ET1 bit in the IE register (Section "15.2. Interrupt Register Descriptions" on page 91). Both counter/timers operate in one of four primary modes selected by setting the Mode Select bits T1M1-T0M0 in the Counter/Timer Mode register (TMOD). Each timer can be configured independently. Each operating mode is described below. 24.1.1. Mode 0: 13-bit Counter/Timer Timer 0 and Timer 1 operate as 13-bit counter/timers in Mode 0. The following describes the configuration and operation of Timer 0. However, both timers operate identically, and Timer 1 is configured in the same manner as described for Timer 0. The TH0 register holds the eight MSBs of the 13-bit counter/timer. TL0 holds the five LSBs in bit positions TL0.4-TL0.0. The three upper bits of TL0 (TL0.7-TL0.5) are indeterminate and should be masked out or ignored when reading. As the 13-bit timer register increments and overflows from 0x1FFF (all ones) to 0x0000, the timer overflow flag TF0 (TCON.5) is set and an interrupt will occur if Timer 0 interrupts are enabled. The C/T0 bit (TMOD.2) selects the counter/timer's clock source. When C/T0 is set to logic 1, high-to-low transitions at the selected Timer 0 input pin (T0) increment the timer register (Refer to Section "20.3. Priority Crossbar Decoder" on page 131 for information on selecting and configuring external I/O pins). Clearing C/T selects the clock defined by the T0M bit (CKCON.3). When T0M is set, Timer 0 is clocked by the system clock. When T0M is cleared, Timer 0 is clocked by the source selected by the Clock Scale bits in CKCON (see SFR Definition 24.1). Setting the TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or the input signal /INT0 is active as defined by bit IN0PL in register IT01CF (see SFR Definition 15.5). Setting GATE0 to `1' allows the timer to be controlled by the external input signal /INT0 (see Section "15.2. Interrupt Register Descriptions" on page 91), facilitating pulse width measurements TR0 0 1 1 1 GATE0 X 0 1 1 /INT0 X X 0 1 Counter/Timer Disabled Enabled Disabled Enabled Note: X = Don't Care Setting TR0 does not force the timer to reset. The timer registers should be loaded with the desired initial value before the timer is enabled. TL1 and TH1 form the 13-bit register for Timer 1 in the same manner as described above for TL0 and TH0. Timer 1 is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0. The input signal /INT1 is used with Timer 1; the /INT1 polarity is defined by bit IN1PL in register IT01CF (see SFR Definition 15.5). Rev. 0.2 189 C8051F336/7/8/9 CKCON T 3 M H T 3 M L T 2 M H TTTSS 2 1 0CC MMMA A 10 L G A T E 1 C / T 1 TM OD T 1 M 1 T 1 M 0 G A T E 0 C / T 0 T 0 M 1 T 0 M 0 I N 1 P L I N 1 S L 2 IT 0 1 C F I N 1 S L 1 I N 1 S L 0 I N 0 P L I N 0 S L 2 I N 0 S L 1 I N 0 S L 0 P re -s c a le d C lo c k 0 0 SYS C LK 1 1 T0 TR 0 G ATE0 C ro s s b a r TCLK /IN T 0 IN 0 P L XO R Figure 24.1. T0 Mode 0 Block Diagram 24.1.2. Mode 1: 16-bit Counter/Timer Mode 1 operation is the same as Mode 0, except that the counter/timer registers use all 16 bits. The counter/timers are enabled and configured in Mode 1 in the same manner as for Mode 0. 190 Rev. 0.2 TCON TL0 (5 b its ) TH 0 (8 b its ) TF1 TR1 TF0 TR0 IE 1 IT 1 IE 0 IT 0 In te rru p t C8051F336/7/8/9 24.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload Mode 2 configures Timer 0 and Timer 1 to operate as 8-bit counter/timers with automatic reload of the start value. TL0 holds the count and TH0 holds the reload value. When the counter in TL0 overflows from all ones to 0x00, the timer overflow flag TF0 (TCON.5) is set and the counter in TL0 is reloaded from TH0. If Timer 0 interrupts are enabled, an interrupt will occur when the TF0 flag is set. The reload value in TH0 is not changed. TL0 must be initialized to the desired value before enabling the timer for the first count to be correct. When in Mode 2, Timer 1 operates identically to Timer 0. Both counter/timers are enabled and configured in Mode 2 in the same manner as Mode 0. Setting the TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or when the input signal /INT0 is active as defined by bit IN0PL in register IT01CF (see Section "15.3. External Interrupts /INT0 and /INT1" on page 96 for details on the external input signals /INT0 and /INT1). CKCON TTTTTTS 332210C MMMMMMA HLHL 1 S C A 0 G A T E 1 C / T 1 TMOD T 1 M 1 T 1 M 0 G A T E 0 C / T 0 T 0 M 1 T 0 M 0 I N 1 P L I N 1 S L 2 IT01CF I N 1 S L 1 I N 1 S L 0 I N 0 P L I N 0 S L 2 I N 0 S L 1 I N 0 S L 0 Pre-scaled Clock 0 0 SYSCLK 1 1 T0 TCLK TL0 (8 bits) TCON TR0 Crossbar GATE0 TH0 (8 bits) /INT0 IN0PL XOR TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Interrupt Reload Figure 24.2. T0 Mode 2 Block Diagram Rev. 0.2 191 C8051F336/7/8/9 24.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only) In Mode 3, Timer 0 is configured as two separate 8-bit counter/timers held in TL0 and TH0. The counter/timer in TL0 is controlled using the Timer 0 control/status bits in TCON and TMOD: TR0, C/T0, GATE0 and TF0. TL0 can use either the system clock or an external input signal as its timebase. The TH0 register is restricted to a timer function sourced by the system clock or prescaled clock. TH0 is enabled using the Timer 1 run control bit TR1. TH0 sets the Timer 1 overflow flag TF1 on overflow and thus controls the Timer 1 interrupt. Timer 1 is inactive in Mode 3. When Timer 0 is operating in Mode 3, Timer 1 can be operated in Modes 0, 1 or 2, but cannot be clocked by external signals nor set the TF1 flag and generate an interrupt. However, the Timer 1 overflow can be used to generate baud rates for the SMBus and/or UART, and/or initiate ADC conversions. While Timer 0 is operating in Mode 3, Timer 1 run control is handled through its mode settings. To run Timer 1 while Timer 0 is in Mode 3, set the Timer 1 Mode as 0, 1, or 2. To disable Timer 1, configure it for Mode 3. CKCON TTTTTTSS 3 3 2 2 1 0 CC MMMMMM A A HLHL 10 G A T E 1 C / T 1 TMOD TT 11 MM 10 G A T E 0 C / T 0 TT 00 MM 10 Pre-scaled Clock 0 TR1 TH0 (8 bits) TCON TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Interrupt Interrupt SYSCLK 1 0 1 T0 TL0 (8 bits) TR0 Crossbar GATE0 /INT0 IN0PL XOR Figure 24.3. T0 Mode 3 Block Diagram 192 Rev. 0.2 C8051F336/7/8/9 SFR Definition 24.2. TCON: Timer Control Bit Name Type Reset 7 TF1 R/W 0 6 TR1 R/W 0 5 TF0 R/W 0 4 TR0 R/W 0 3 IE1 R/W 0 2 IT1 R/W 0 1 IE0 R/W 0 0 IT0 R/W 0 SFR Address = 0x88; Bit-Addressable Bit Name 7 TF1 Timer 1 Overflow Flag. Function Set to `1' by hardware when Timer 1 overflows. This flag can be cleared by software but is automatically cleared when the CPU vectors to the Timer 1 interrupt service routine. 6 5 TR1 TF0 Timer 1 Run Control. Timer 1 is enabled by setting this bit to `1'. Timer 0 Overflow Flag. Set to `1' by hardware when Timer 0 overflows. This flag can be cleared by software but is automatically cleared when the CPU vectors to the Timer 0 interrupt service routine. 4 3 TR0 IE1 Timer 0 Run Control. Timer 0 is enabled by setting this bit to `1'. External Interrupt 1. This flag is set by hardware when an edge/level of type defined by IT1 is detected. It can be cleared by software but is automatically cleared when the CPU vectors to the External Interrupt 1 service routine in edge-triggered mode. 2 IT1 Interrupt 1 Type Select. This bit selects whether the configured /INT1 interrupt will be edge or level sensitive. /INT1 is configured active low or high by the IN1PL bit in the IT01CF register (see SFR Definition 15.5). 0: /INT1 is level triggered. 1: /INT1 is edge triggered. 1 IE0 External Interrupt 0. This flag is set by hardware when an edge/level of type defined by IT1 is detected. It can be cleared by software but is automatically cleared when the CPU vectors to the External Interrupt 0 service routine in edge-triggered mode. 0 IT0 Interrupt 0 Type Select. This bit selects whether the configured /INT0 interrupt will be edge or level sensitive. /INT0 is configured active low or high by the IN0PL bit in register IT01CF (see SFR Definition 15.5). 0: /INT0 is level triggered. 1: /INT0 is edge triggered. Rev. 0.2 193 C8051F336/7/8/9 SFR Definition 24.3. TMOD: Timer Mode Bit Name Type Reset 7 GATE1 R/W 0 6 C/T1 R/W 0 0 5 T1M[1:0] R/W 0 4 3 GATE0 R/W 0 2 C/T0 R/W 0 0 1 T0M[1:0] R/W 0 0 SFR Address = 0x89 Bit Name 7 GATE1 Timer 1 Gate Control. Function 0: Timer 1 enabled when TR1 = 1 irrespective of /INT1 logic level. 1: Timer 1 enabled only when TR1 = 1 AND /INT1 is active as defined by bit IN1PL in register IT01CF (see SFR Definition 15.5). 6 C/T1 Counter/Timer 1 Select. 0: Timer: Timer 1 incremented by clock defined by T1M bit in register CKCON. 1: Counter: Timer 1 incremented by high-to-low transitions on external pin (T1). 5:4 T1M[1:0] Timer 1 Mode Select. These bits select the Timer 1 operation mode. 00: Mode 0, 13-bit Counter/Timer 01: Mode 1, 16-bit Counter/Timer 10: Mode 2, 8-bit Counter/Timer with Auto-Reload 11: Mode 3, Timer 1 Inactive 3 GATE0 Timer 0 Gate Control. 0: Timer 0 enabled when TR0 = 1 irrespective of /INT0 logic level. 1: Timer 0 enabled only when TR0 = 1 AND /INT0 is active as defined by bit IN0PL in register IT01CF (see SFR Definition 15.5). 2 C/T0 Counter/Timer 0 Select. 0: Timer: Timer 0 incremented by clock defined by T0M bit in register CKCON. 1: Counter: Timer 0 incremented by high-to-low transitions on external pin (T0). 1:0 T0M[1:0] Timer 0 Mode Select. These bits select the Timer 0 operation mode. 00: Mode 0, 13-bit Counter/Timer 01: Mode 1, 16-bit Counter/Timer 10: Mode 2, 8-bit Counter/Timer with Auto-Reload 11: Mode 3, Two 8-bit Counter/Timers 194 Rev. 0.2 C8051F336/7/8/9 SFR Definition 24.4. TL0: Timer 0 Low Byte Bit Name Type Reset 0 0 0 0 7 6 5 4 TL0[7:0] R/W 0 0 0 0 3 2 1 0 SFR Address = 0x8A Bit Name 7:0 TL0[7:0] Timer 0 Low Byte. Function The TL0 register is the low byte of the 16-bit Timer 0. SFR Definition 24.5. TL1: Timer 1 Low Byte Bit Name Type Reset 0 0 0 0 7 6 5 4 TL1[7:0] R/W 0 0 0 0 3 2 1 0 SFR Address = 0x8B Bit Name 7:0 TL1[7:0] Timer 1 Low Byte. Function The TL1 register is the low byte of the 16-bit Timer 1. Rev. 0.2 195 C8051F336/7/8/9 SFR Definition 24.6. TH0: Timer 0 High Byte Bit Name Type Reset 0 0 0 0 7 6 5 4 TH0[7:0] R/W 0 0 0 0 3 2 1 0 SFR Address = 0x8C Bit Name 7:0 TH0[7:0] Timer 0 High Byte. Function The TH0 register is the high byte of the 16-bit Timer 0. SFR Definition 24.7. TH1: Timer 1 High Byte Bit Name Type Reset 0 0 0 0 7 6 5 4 TH1[7:0] R/W 0 0 0 0 3 2 1 0 SFR Address = 0x8D Bit Name 7:0 TH1[7:0] Timer 1 High Byte. Function The TH1 register is the high byte of the 16-bit Timer 1. 196 Rev. 0.2 C8051F336/7/8/9 24.2. Timer 2 Timer 2 is a 16-bit timer formed by two 8-bit SFRs: TMR2L (low byte) and TMR2H (high byte). Timer 2 may operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T2SPLIT bit (TMR2CN.3) defines the Timer 2 operation mode. Timer 2 may be clocked by the system clock, the system clock divided by 12, or the external oscillator source divided by 8. The external clock mode is ideal for real-time clock (RTC) functionality, where the internal oscillator drives the system clock while Timer 2 (and/or the PCA) is clocked by an external precision oscillator. Note that the external oscillator source divided by 8 is synchronized with the system clock. 24.2.1. 16-bit Timer with Auto-Reload When T2SPLIT (TMR2CN.3) is zero, Timer 2 operates as a 16-bit timer with auto-reload. Timer 2 can be clocked by SYSCLK, SYSCLK divided by 12, or the external oscillator clock source divided by 8. As the 16-bit timer register increments and overflows from 0xFFFF to 0x0000, the 16-bit value in the Timer 2 reload registers (TMR2RLH and TMR2RLL) is loaded into the Timer 2 register as shown in Figure 24.4, and the Timer 2 High Byte Overflow Flag (TMR2CN.7) is set. If Timer 2 interrupts are enabled (if IE.5 is set), an interrupt will be generated on each Timer 2 overflow. Additionally, if Timer 2 interrupts are enabled and the TF2LEN bit is set (TMR2CN.5), an interrupt will be generated each time the lower 8 bits (TMR2L) overflow from 0xFF to 0x00. CKCON T2XCLK TTTTTTS 332210C MMMMMMA HLHL 1 S C A 0 To SMBus To ADC, SMBus SYSCLK / 12 0 0 TR2 TCLK TL2 Overflow External Clock / 8 SYSCLK 1 TMR2CN 1 TMR2L TMR2H TF2H TF2L TF2LEN TF2CEN T2SPLIT TR2 T2XCLK Interrupt TMR2RLL TMR2RLH Reload Figure 24.4. Timer 2 16-Bit Mode Block Diagram Rev. 0.2 197 C8051F336/7/8/9 24.2.2. 8-bit Timers with Auto-Reload When T2SPLIT is set, Timer 2 operates as two 8-bit timers (TMR2H and TMR2L). Both 8-bit timers operate in auto-reload mode as shown in Figure 24.5. TMR2RLL holds the reload value for TMR2L; TMR2RLH holds the reload value for TMR2H. The TR2 bit in TMR2CN handles the run control for TMR2H. TMR2L is always running when configured for 8-bit Mode. Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, or the external oscillator clock source divided by 8. The Timer 2 Clock Select bits (T2MH and T2ML in CKCON) select either SYSCLK or the clock defined by the Timer 2 External Clock Select bit (T2XCLK in TMR2CN), as follows: T2MH 0 0 1 T2XCLK 0 1 X TMR2H Clock Source SYSCLK / 12 External Clock / 8 SYSCLK T2ML 0 0 1 T2XCLK 0 1 X TMR2L Clock Source SYSCLK / 12 External Clock / 8 SYSCLK The TF2H bit is set when TMR2H overflows from 0xFF to 0x00; the TF2L bit is set when TMR2L overflows from 0xFF to 0x00. When Timer 2 interrupts are enabled (IE.5), an interrupt is generated each time TMR2H overflows. If Timer 2 interrupts are enabled and TF2LEN (TMR2CN.5) is set, an interrupt is generated each time either TMR2L or TMR2H overflows. When TF2LEN is enabled, software must check the TF2H and TF2L flags to determine the source of the Timer 2 interrupt. The TF2H and TF2L interrupt flags are not cleared by hardware and must be manually cleared by software. CKCON T2XCLK TTTTTTS 332210C MMMMMMA HLHL 1 S C A 0 TMR2RLH Reload To SMBus SYSCLK / 12 0 0 External Clock / 8 1 TR2 1 TCLK TMR2H TMR2CN TMR2RLL SYSCLK Reload TF2H TF2L TF2LEN TF2CEN T2SPLIT TR2 T2XCLK Interrupt 1 TCLK 0 TMR2L To ADC, SMBus Figure 24.5. Timer 2 8-Bit Mode Block Diagram 198 Rev. 0.2 C8051F336/7/8/9 24.2.3. Low-Frequency Oscillator (LFO) Capture Mode The Low-Frequency Oscillator Capture Mode allows the LFO clock to be measured against the system clock or an external oscillator source. Timer 2 can be clocked from the system clock, the system clock divided by 12, or the external oscillator divided by 8, depending on the T2ML (CKCON.4), and T2XCLK settings. Setting TF2CEN to `1' enables the LFO Capture Mode for Timer 2. In this mode, T2SPLIT should be set to `0', as the full 16-bit timer is used. Upon a falling edge of the low-frequency oscillator, the contents of Timer 2 (TMR2H:TMR2L) are loaded into the Timer 2 reload registers (TMR2RLH:TMR2RLL) and the TF2H flag is set. By recording the difference between two successive timer capture values, the LFO clock frequency can be determined with respect to the Timer 2 clock. The Timer 2 clock should be much faster than the LFO to achieve an accurate reading. CKCON T2XCLK TTTTTTSS 3 3 2 2 1 0 CC MMMMMM A A HLHL 10 SYSCLK / 12 0 0 TR2 TCLK External Clock / 8 SYSCLK 1 1 Capture TMR2L TMR2H TMR2CN Low-Frequency Oscillator TF2CEN TMR2RLL TMR2RLH TF2H TF2L TF2LEN TF2CEN T2SPLIT TR2 T2XCLK Interrupt Figure 24.6. Timer 2 Low-Frequency Oscillation Capture Mode Block Diagram Rev. 0.2 199 C8051F336/7/8/9 SFR Definition 24.8. TMR2CN: Timer 2 Control Bit Name Type Reset 7 TF2H R/W 0 6 TF2L R/W 0 5 TF2LEN R/W 0 4 TF2CEN R/W 0 3 T2SPLIT R/W 0 2 TR2 R/W 0 R 0 1 0 T2XCLK R/W 0 SFR Address = 0xC8; Bit-Addressable Bit Name 7 TF2H Timer 2 High Byte Overflow Flag. Function Set by hardware when the Timer 2 high byte overflows from 0xFF to 0x00. In 16 bit mode, this will occur when Timer 2 overflows from 0xFFFF to 0x0000. When the Timer 2 interrupt is enabled, setting this bit causes the CPU to vector to the Timer 2 interrupt service routine. This bit is not automatically cleared by hardware. 6 TF2L Timer 2 Low Byte Overflow Flag. Set by hardware when the Timer 2 low byte overflows from 0xFF to 0x00. TF2L will be set when the low byte overflows regardless of the Timer 2 mode. This bit is not automatically cleared by hardware. 5 TF2LEN Timer 2 Low Byte Interrupt Enable. When set to `1', this bit enables Timer 2 Low Byte interrupts. If Timer 2 interrupts are also enabled, an interrupt will be generated when the low byte of Timer 2 overflows. 4 TF2CEN Timer 2 Low-Frequency Oscillator Capture Enable. When set to `1', this bit enables Timer 2 Low-Frequency Oscillator Capture Mode. If TF2CEN is set and Timer 2 interrupts are enabled, an interrupt will be generated on a falling edge of the low-frequency oscillator output, and the current 16-bit timer value in TMR2H:TMR2L will be copied to TMR2RLH:TMR2RLL. 3 T2SPLIT Timer 2 Split Mode Enable. When this bit is set, Timer 2 operates as two 8-bit timers with auto-reload. 0: Timer 2 operates in 16-bit auto-reload mode. 1: Timer 2 operates as two 8-bit auto-reload timers. 2 TR2 Timer 2 Run Control. Timer 2 is enabled by setting this bit to `1'. In 8-bit mode, this bit enables/disables TMR2H only; TMR2L is always enabled in split mode. 1 0 UNUSED T2XCLK Unused. Read = 0b; Write = Don't Care Timer 2 External Clock Select. This bit selects the external clock source for Timer 2. If Timer 2 is in 8-bit mode, this bit selects the external oscillator clock source for both timer bytes. However, the Timer 2 Clock Select bits (T2MH and T2ML in register CKCON) may still be used to select between the external clock and the system clock for either timer. 0: Timer 2 clock is the system clock divided by 12. 1: Timer 2 clock is the external clock divided by 8 (synchronized with SYSCLK). 200 Rev. 0.2 C8051F336/7/8/9 SFR Definition 24.9. TMR2RLL: Timer 2 Reload Register Low Byte Bit Name Type Reset 0 0 0 0 7 6 5 4 3 2 1 0 TMR2RLL[7:0] R/W 0 0 0 0 SFR Address = 0xCA Bit Name 7:0 Function TMR2RLL holds the low byte of the reload value for Timer 2. TMR2RLL[7:0] Timer 2 Reload Register Low Byte. SFR Definition 24.10. TMR2RLH: Timer 2 Reload Register High Byte Bit Name Type Reset 0 0 0 0 7 6 5 4 3 2 1 0 TMR2RLH[7:0] R/W 0 0 0 0 SFR Address = 0xCB Bit Name Function TMR2RLH holds the high byte of the reload value for Timer 2. 7:0 TMR2RLH[7:0] Timer 2 Reload Register High Byte. SFR Definition 24.11. TMR2L: Timer 2 Low Byte Bit Name Type Reset 0 0 0 0 7 6 5 4 3 2 1 0 TMR2L[7:0] R/W 0 0 0 0 SFR Address = 0xCC Bit Name 7:0 TMR2L[7:0] Timer 2 Low Byte. Function In 16-bit mode, the TMR2L register contains the low byte of the 16-bit Timer 2. In 8bit mode, TMR2L contains the 8-bit low byte timer value. Rev. 0.2 201 C8051F336/7/8/9 SFR Definition 24.12. TMR2H Timer 2 High Byte Bit Name Type Reset 0 0 0 0 7 6 5 4 3 2 1 0 TMR2H[7:0] R/W 0 0 0 0 SFR Address = 0xCD Bit Name 7:0 TMR2H[7:0] Timer 2 Low Byte. Function In 16-bit mode, the TMR2H register contains the high byte of the 16-bit Timer 2. In 8bit mode, TMR2H contains the 8-bit high byte timer value. 202 Rev. 0.2 C8051F336/7/8/9 24.3. Timer 3 Timer 3 is a 16-bit timer formed by two 8-bit SFRs: TMR3L (low byte) and TMR3H (high byte). Timer 3 may operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T3SPLIT bit (TMR3CN.3) defines the Timer 3 operation mode. Timer 3 may be clocked by the system clock, the system clock divided by 12, the external oscillator source divided by 8, or the internal low-frequency oscillator divided by 8. The external clock mode is ideal for realtime clock (RTC) functionality, where the internal high-frequency oscillator drives the system clock while Timer 3 is clocked by an external oscillator source. Note that the external oscillator source divided by 8 and the LFO source divided by 8 are synchronized with the system clock when in all operating modes except suspend. When the internal oscillator is placed in suspend mode, The external clock / 8 signal or the LFO / 8 output can directly drive the timer. This allows the use of an external clock or the LFO to wake up the device from suspend mode. The timer will continue to run in suspend mode and count up. When the timer overflow occurs, the device will wake from suspend mode, and begin executing code again. The timer value may be set prior to entering suspend, to overflow in the desired amount of time (number of clocks) to wake the device. If a wake-up source other than the timer wakes the device from suspend mode, it may take up to three timer clocks before the timer registers can be read or written. During this time, the STSYNC bit in register OSCICN will be set to '1', to indicate that it is not safe to read or write the timer registers. Important Note: In internal LFO / 8 mode, the divider for the internal LFO must be set to 1 for proper functionality. The timer will not operate if the LFO divider is not set to 1. 24.3.1. 16-bit Timer with Auto-Reload When T3SPLIT (TMR3CN.3) is zero, Timer 3 operates as a 16-bit timer with auto-reload. Timer 3 can be clocked by SYSCLK, SYSCLK divided by 12, or the external oscillator clock source divided by 8. As the 16-bit timer register increments and overflows from 0xFFFF to 0x0000, the 16-bit value in the Timer 3 reload registers (TMR3RLH and TMR3RLL) is loaded into the Timer 3 register as shown in Figure 24.7, and the Timer 3 High Byte Overflow Flag (TMR3CN.7) is set. If Timer 3 interrupts are enabled (if EIE1.7 is set), an interrupt will be generated on each Timer 3 overflow. Additionally, if Timer 3 interrupts are enabled and the TF3LEN bit is set (TMR3CN.5), an interrupt will be generated each time the lower 8 bits (TMR3L) overflow from 0xFF to 0x00. CKCON T3XCLK[1:0] TTTTTTS 332210C MMMMMMA HLHL 1 S C A 0 SYSCLK / 12 External Clock / 8 Internal LFO / 8 00 To ADC 01 11 0 TR3 TCLK TMR3L TMR3H TMR3CN 1 SYSCLK TMR3RLL TMR3RLH Reload TF3H TF3L TF3LEN TF3CEN T3SPLIT TR3 T3XCLK1 T3XCLK0 Interrupt Figure 24.7. Timer 3 16-Bit Mode Block Diagram Rev. 0.2 203 C8051F336/7/8/9 24.3.2. 8-bit Timers with Auto-Reload When T3SPLIT is set, Timer 3 operates as two 8-bit timers (TMR3H and TMR3L). Both 8-bit timers operate in auto-reload mode as shown in Figure 24.8. TMR3RLL holds the reload value for TMR3L; TMR3RLH holds the reload value for TMR3H. The TR3 bit in TMR3CN handles the run control for TMR3H. TMR3L is always running when configured for 8-bit Mode. Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, the external oscillator clock source divided by 8, or the internal Low-frequency Oscillator. The Timer 3 Clock Select bits (T3MH and T3ML in CKCON) select either SYSCLK or the clock defined by the Timer 3 External Clock Select bits (T3XCLK[1:0] in TMR3CN), as follows: T3MH 0 0 0 0 1 T3XCLK[1:0] 00 01 10 11 X TMR3H Clock Source SYSCLK / 12 External Clock / 8 Reserved Internal LFO SYSCLK T3ML 0 0 0 0 1 T3XCLK[1:0] 00 01 10 11 X TMR3L Clock Source SYSCLK / 12 External Clock / 8 Reserved Internal LFO SYSCLK The TF3H bit is set when TMR3H overflows from 0xFF to 0x00; the TF3L bit is set when TMR3L overflows from 0xFF to 0x00. When Timer 3 interrupts are enabled, an interrupt is generated each time TMR3H overflows. If Timer 3 interrupts are enabled and TF3LEN (TMR3CN.5) is set, an interrupt is generated each time either TMR3L or TMR3H overflows. When TF3LEN is enabled, software must check the TF3H and TF3L flags to determine the source of the Timer 3 interrupt. The TF3H and TF3L interrupt flags are not cleared by hardware and must be manually cleared by software. CKCON T3XCLK[1:0] TTTTTTSS 3 3 2 2 1 0CC MMMMMM A A HLHL 10 TMR3RLH Reload SYSCLK / 12 External Clock / 8 Internal LFO / 8 00 0 01 TR3 11 1 Reload TMR3CN TCLK TMR3H TF3H TF3L TF3LEN TF3CEN T3SPLIT TR3 T3XCLK1 T3XCLK0 Interrupt TMR3RLL SYSCLK 1 TCLK 0 TMR3L To ADC Figure 24.8. Timer 3 8-Bit Mode Block Diagram 204 Rev. 0.2 C8051F336/7/8/9 24.3.3. Low-Frequency Oscillator (LFO) Capture Mode The Low-Frequency Oscillator Capture Mode allows the LFO clock to be measured against the system clock or an external oscillator source. Timer 3 can be clocked from the system clock, the system clock divided by 12, or the external oscillator divided by 8, depending on the T3ML (CKCON.6), and T3XCLK[1:0] settings. Setting TF3CEN to `1' enables the LFO Capture Mode for Timer 3. In this mode, T3SPLIT should be set to `0', as the full 16-bit timer is used. Upon a falling edge of the low-frequency oscillator, the contents of Timer 3 (TMR3H:TMR3L) are loaded into the Timer 3 reload registers (TMR3RLH:TMR3RLL) and the TF3H flag is set. By recording the difference between two successive timer capture values, the LFO clock frequency can be determined with respect to the Timer 3 clock. The Timer 3 clock should be much faster than the LFO to achieve an accurate reading. This means that the LFO / 8 should not be selected as the timer clock source in this mode. CKCON T3XCLK[1:0] TTTTTTSS 3 3 2 2 1 0 CC MMMMMM A A HLHL 10 SYSCLK / 12 00 0 TR3 TCLK External Clock / 8 SYSCLK 01 1 Capture TMR3L TMR3H Figure 24.9. Timer 3 Low-Frequency Oscillation Capture Mode Block Diagram Rev. 0.2 TMR3CN Low-Frequency Oscillator TF3CEN TMR3RLL TMR3RLH TF3H TF3L TF3LEN TF3CEN T3SPLIT TR3 T3XCLK1 T3XCLK0 Interrupt 205 C8051F336/7/8/9 SFR Definition 24.13. TMR3CN: Timer 3 Control Bit Name Type Reset 7 TF3H R/W 0 6 TF3L R/W 0 5 TF3LEN R/W 0 4 TF3CEN R/W 0 3 T3SPLIT R/W 0 2 TR3 R/W 0 0 1 0 T3XCLK[1:0] R/W 0 SFR Address = 0x91 Bit Name 7 TF3H Timer 3 High Byte Overflow Flag. Function Set by hardware when the Timer 3 high byte overflows from 0xFF to 0x00. In 16 bit mode, this will occur when Timer 3 overflows from 0xFFFF to 0x0000. When the Timer 3 interrupt is enabled, setting this bit causes the CPU to vector to the Timer 3 interrupt service routine. This bit is not automatically cleared by hardware. 6 TF3L Timer 3 Low Byte Overflow Flag. Set by hardware when the Timer 3 low byte overflows from 0xFF to 0x00. TF3L will be set when the low byte overflows regardless of the Timer 3 mode. This bit is not automatically cleared by hardware. 5 TF3LEN Timer 3 Low Byte Interrupt Enable. When set to `1', this bit enables Timer 3 Low Byte interrupts. If Timer 3 interrupts are also enabled, an interrupt will be generated when the low byte of Timer 3 overflows. 4 TF3CEN Timer 3 Low-Frequency Oscillator Capture Enable. When set to `1', this bit enables Timer 3 Low-Frequency Oscillator Capture Mode. If TF3CEN is set and Timer 3 interrupts are enabled, an interrupt will be generated on a falling edge of the low-frequency oscillator output, and the current 16-bit timer value in TMR3H:TMR3L will be copied to TMR3RLH:TMR3RLL. 3 T3SPLIT Timer 3 Split Mode Enable. When this bit is set, Timer 3 operates as two 8-bit timers with auto-reload. 0: Timer 3 operates in 16-bit auto-reload mode. 1: Timer 3 operates as two 8-bit auto-reload timers. 2 TR3 Timer 3 Run Control. Timer 3 is enabled by setting this bit to `1'. In 8-bit mode, this bit enables/disables TMR3H only; TMR3L is always enabled in split mode. 1:0 T3XCLK[1:0] Timer 3 External Clock Select. This bit selects the "external" clock source for Timer 3. If Timer 3 is in 8-bit mode, this bit selects the external oscillator clock source for both timer bytes. However, the Timer 3 Clock Select bits (T3MH and T3ML in register CKCON) may still be used to select between the external clock and the system clock for either timer. 00: System clock divided by 12. 01: External clock divided by 8 (synchronized with SYSCLK when not in suspend). 10: Reserved. 11: Internal LFO / 8 (synchronized with SYSCLK when not in suspend). 206 Rev. 0.2 C8051F336/7/8/9 SFR Definition 24.14. TMR3RLL: Timer 3 Reload Register Low Byte Bit Name Type Reset 0 0 0 0 7 6 5 4 3 2 1 0 TMR3RLL[7:0] R/W 0 0 0 0 SFR Address = 0x92 Bit Name 7:0 Function TMR3RLL holds the low byte of the reload value for Timer 3. TMR3RLL[7:0] Timer 3 Reload Register Low Byte. SFR Definition 24.15. TMR3RLH: Timer 3 Reload Register High Byte Bit Name Type Reset 0 0 0 0 7 6 5 4 3 2 1 0 TMR3RLH[7:0] R/W 0 0 0 0 SFR Address = 0x93 Bit Name Function TMR3RLH holds the high byte of the reload value for Timer 3. 7:0 TMR3RLH[7:0] Timer 3 Reload Register High Byte. SFR Definition 24.16. TMR3L: Timer 3 Low Byte Bit Name Type Reset 0 0 0 0 7 6 5 4 3 2 1 0 TMR3L[7:0] R/W 0 0 0 0 SFR Address = 0x94 Bit Name 7:0 TMR3L[7:0] Timer 3 Low Byte. Function In 16-bit mode, the TMR3L register contains the low byte of the 16-bit Timer 3. In 8-bit mode, TMR3L contains the 8-bit low byte timer value. Rev. 0.2 207 C8051F336/7/8/9 SFR Definition 24.17. TMR3H Timer 3 High Byte Bit Name Type Reset 0 0 0 0 7 6 5 4 3 2 1 0 TMR3H[7:0] R/W 0 0 0 0 SFR Address = 0x95 Bit Name 7:0 TMR3H[7:0] Timer 3 High Byte. Function In 16-bit mode, the TMR3H register contains the high byte of the 16-bit Timer 3. In 8-bit mode, TMR3H contains the 8-bit high byte timer value. 208 Rev. 0.2 C8051F336/7/8/9 25. Programmable Counter Array The Programmable Counter Array (PCA0) provides enhanced timer functionality while requiring less CPU intervention than the standard 8051 counter/timers. The PCA consists of a dedicated 16-bit counter/timer and three 16-bit capture/compare modules. Each capture/compare module has its own associated I/O line (CEXn) which is routed through the Crossbar to Port I/O when enabled. The counter/timer is driven by a programmable timebase that can select between six sources: system clock, system clock divided by four, system clock divided by twelve, the external oscillator clock source divided by 8, Timer 0 overflows, or an external clock signal on the ECI input pin. Each capture/compare module may be configured to operate independently in one of six modes: Edge-Triggered Capture, Software Timer, High-Speed Output, Frequency Output, 8 to 11-Bit PWM, or 16-Bit PWM (each mode is described in Section "25.3. Capture/Compare Modules" on page 212). The external oscillator clock option is ideal for real-time clock (RTC) functionality, allowing the PCA to be clocked by a precision external oscillator while the internal oscillator drives the system clock. The PCA is configured and controlled through the system controller's Special Function Registers. The PCA block diagram is shown in Figure 25.1 Important Note: The PCA Module 2 may be used as a watchdog timer (WDT), and is enabled in this mode following a system reset. Access to certain PCA registers is restricted while WDT mode is enabled. See Section 25.4 for details. SYSCLK/12 SYSCLK/4 Timer 0 Overflow ECI SYSCLK External Clock/8 PCA CLOCK MUX 16-Bit Counter/Timer Capture/Compare Module 0 Capture/Compare Module 1 Capture/Compare Module 2 / WDT CEX0 CEX1 CEX2 ECI Crossbar Port I/O Figure 25.1. PCA Block Diagram Rev. 0.2 209 C8051F336/7/8/9 25.1. PCA Counter/Timer The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte (MSB) of the 16-bit counter/timer and PCA0L is the low byte (LSB). Reading PCA0L automatically latches the value of PCA0H into a "snapshot" register; the following PCA0H read accesses this "snapshot" register. Reading the PCA0L Register first guarantees an accurate reading of the entire 16-bit PCA0 counter. Reading PCA0H or PCA0L does not disturb the counter operation. The CPS2-CPS0 bits in the PCA0MD register select the timebase for the counter/timer as shown in Table 25.1. When the counter/timer overflows from 0xFFFF to 0x0000, the Counter Overflow Flag (CF) in PCA0MD is set to logic 1 and an interrupt request is generated if CF interrupts are enabled. Setting the ECF bit in PCA0MD to logic 1 enables the CF flag to generate an interrupt request. The CF bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by software. Clearing the CIDL bit in the PCA0MD register allows the PCA to continue normal operation while the CPU is in Idle mode. Table 25.1. PCA Timebase Input Options CPS2 0 0 0 0 1 1 1 CPS1 0 0 1 1 0 0 1 CPS0 0 1 0 1 0 1 x Timebase System clock divided by 12 System clock divided by 4 Timer 0 overflow High-to-low transitions on ECI (max rate = system clock divided by 4) System clock External oscillator source divided by 8* Reserved *Note: External oscillator source divided by 8 is synchronized with the system clock. IDLE PCA0MD CWW I DD DTL LEC K CCCE PPPC SSSF 210 PCA0CN CC FR CCC CCC FFF 210 PCA0L read To SFR Bus Snapshot Register SYSCLK/12 SYSCLK/4 Timer 0 Overflow ECI SYSCLK External Clock/8 000 001 010 011 100 101 0 1 PCA0H PCA0L Overflow CF To PCA Modules To PCA Interrupt System Figure 25.2. PCA Counter/Timer Block Diagram 210 Rev. 0.2 C8051F336/7/8/9 25.2. PCA0 Interrupt Sources Figure 25.3 shows a diagram of the PCA interrupt tree. There are five independent event flags that can be used to generate a PCA0 interrupt. They are: the main PCA counter overflow flag (CF), which is set upon a 16-bit overflow of the PCA0 counter, an intermediate overflow flag (COVF), which can be set on an overflow from the 8th, 9th, 10th, or 11th bit of the PCA0 counter, and the individual flags for each PCA channel (CCF0, CCF1, and CCF2), which are set according to the operation mode of that module. These event flags are always set when the trigger condition occurs. Each of these flags can be individually selected to generate a PCA0 interrupt, using the corresponding interrupt enable flag (ECF for CF, ECOV for COVF, and ECCFn for each CCFn). PCA0 interrupts must be globally enabled before any individual interrupt sources are recognized by the processor. PCA0 interrupts are globally enabled by setting the EA bit and the EPCA0 bit to logic 1. (for n = 0 to 2) PCA0CPMn P ECCMT P E WC A A AOWC MOPP TGMC 1 MP N n n n F 6nnn n n PCA Counter/Timer 8, 9, 10 or 11-bit Overflow PCA Counter/Timer 16bit Overflow PCA0CN CC FR CCC CCC FFF 210 PCA0MD C WW I DD DTL LEC K CCCE PPPC SSSF 210 A R S E L PCA0PWM CE OC VO FV C L S E L 1 C L S E L 0 Set 8, 9, 10, or 11 bit Operation 0 1 0 1 ECCF0 EPCA0 0 1 EA 0 1 PCA Module 0 (CCF0) ECCF1 0 1 Interrupt Priority Decoder PCA Module 1 (CCF1) ECCF2 0 1 PCA Module 2 (CCF2) 0 1 Figure 25.3. PCA Interrupt Block Diagram Rev. 0.2 211 C8051F336/7/8/9 25.3. Capture/Compare Modules Each module can be configured to operate independently in one of six operation modes: Edge-triggered Capture, Software Timer, High Speed Output, Frequency Output, 8 to 11-Bit Pulse Width Modulator, or 16Bit Pulse Width Modulator. Each module has Special Function Registers (SFRs) associated with it in the CIP-51 system controller. These registers are used to exchange data with a module and configure the module's mode of operation. Table 25.2 summarizes the bit settings in the PCA0CPMn and PCA0PWM registers used to select the PCA capture/compare module's operating mode. Note that all modules set to use 8, 9, 10, or 11-bit PWM mode must use the same cycle length (8-11 bits). Setting the ECCFn bit in a PCA0CPMn register enables the module's CCFn interrupt. Table 25.2. PCA0CPM and PCA0PWM Bit Settings for PCA Capture/Compare Modules Operational Mode Capture triggered by positive edge on CEXn Capture triggered by negative edge on CEXn Capture triggered by any transition on CEXn Software Timer High Speed Output Frequency Output 8-Bit Pulse Width Modulator (Note 7) 9-Bit Pulse Width Modulator (Note 7) 10-Bit Pulse Width Modulator (Note 7) 11-Bit Pulse Width Modulator (Note 7) 16-Bit Pulse Width Modulator PCA0CPMn PCA0PWM 4-2 1-0 XX XX XX XX XX XX 00 01 10 11 XX Bit Number 7 6 5 4 3 2 1 0 7 6 5 X X 1 0 0 0 0 A 0 X B XXX X X 0 1 0 0 0 A 0 X B XXX X X 1 1 0 0 0 A 0 X B XXX X C 0 0 1 0 0 A 0 X B XXX X C 0 0 1 1 0 A 0 X B XXX X C 0 0 0 1 1 A 0 X B XXX 0 C 0 0 E 0 1 A 0 X B XXX 0 C 0 0 E 0 1 A D X B XXX 0 C 0 0 E 0 1 A D X B XXX 0 C 0 0 E 0 1 A D X B XXX 1 C 0 0 E 0 1 A 0 X B XXX Notes: 1. X = Don't Care (no functional difference for individual module if 1 or 0). 2. A = Enable interrupts for this module (PCA interrupt triggered on CCFn set to `1'). 3. B = Enable 8th, 9th, 10th or 11th bit overflow interrupt (Depends on setting of CLSEL[1:0]). 4. C = When set to `0', the digital comparator is off. For high speed and frequency output modes, the associated pin will not toggle. In any of the PWM modes, this generates a 0% duty cycle (output = 0). 5. D = Selects whether the Capture/Compare register (0) or the Auto-Reload register (1) for the associated channel is accessed via addresses PCA0CPHn and PCA0CPLn. 6. E = When set, a match event will cause the CCFn flag for the associated channel to be set. 7. All modules set to 8, 9, 10 or 11-bit PWM mode use the same cycle length setting. 212 Rev. 0.2 C8051F336/7/8/9 25.3.1. Edge-triggered Capture Mode In this mode, a valid transition on the CEXn pin causes the PCA to capture the value of the PCA counter/timer and load it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and PCA0CPHn). The CAPPn and CAPNn bits in the PCA0CPMn register are used to select the type of transition that triggers the capture: low-to-high transition (positive edge), high-to-low transition (negative edge), or either transition (positive or negative edge). When a capture occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic 1. An interrupt request is generated if the CCFn interrupt for that module is enabled. The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by software. If both CAPPn and CAPNn bits are set to logic 1, then the state of the Port pin associated with CEXn can be read directly to determine whether a rising-edge or falling-edge caused the capture. PCA Interrupt PCA0CPMn P ECCMT P E WC A A AOWC MOPP TGMC 1 MP N n n n F 6nnn n n xx 000x PCA0CN CC FR CCC CCC FFF 210 (to CCFn) PCA0CPLn PCA0CPHn 0 Port I/O Crossbar CEXn 1 0 1 PCA Timebase Capture PCA0L PCA0H Figure 25.4. PCA Capture Mode Diagram Note: The CEXn input signal must remain high or low for at least 2 system clock cycles to be recognized by the hardware. Rev. 0.2 213 C8051F336/7/8/9 25.3.2. Software Timer (Compare) Mode In Software Timer mode, the PCA counter/timer value is compared to the module's 16-bit capture/compare register (PCA0CPHn and PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic 1. An interrupt request is generated if the CCFn interrupt for that module is enabled. The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by software. Setting the ECOMn and MATn bits in the PCA0CPMn register enables Software Timer mode. Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn bit to `0'; writing to PCA0CPHn sets ECOMn to `1'. Write to PCA0CPLn Reset Write to PCA0CPHn 0 ENB ENB PCA Interrupt 1 PCA0CPMn P ECCMT P E WC A A AOWC MOPP TGMC 1 MP N n n n F 6nnn n n x 00 00x Enable Match 0 1 PCA0CN PCA0CPLn PCA0CPHn CC FR CCC CCC FFF 210 16-bit Comparator PCA Timebase PCA0L PCA0H Figure 25.5. PCA Software Timer Mode Diagram 214 Rev. 0.2 C8051F336/7/8/9 25.3.3. High-Speed Output Mode In High-Speed Output mode, a module's associated CEXn pin is toggled each time a match occurs between the PCA Counter and the module's 16-bit capture/compare register (PCA0CPHn and PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic 1. An interrupt request is generated if the CCFn interrupt for that module is enabled. The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by software. Setting the TOGn, MATn, and ECOMn bits in the PCA0CPMn register enables the HighSpeed Output mode. If ECOMn is cleared, the associated pin will retain its state, and not toggle on the next match event. Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn bit to `0'; writing to PCA0CPHn sets ECOMn to `1'. Write to PCA0CPLn Reset Write to PCA0CPHn 0 ENB PCA0CPMn ENB 1 P ECCMT P E WC A A AOWC MOPP TGMC 1 MPN n n n F 6nnn n n x 00 0x PCA Interrupt PCA0CN PCA0CPLn PCA0CPHn CC FR CCC CCC FFF 210 Enable 16-bit Comparator Match 0 1 TOGn Toggle 0 CEXn 1 Crossbar Port I/O PCA Timebase PCA0L PCA0H Figure 25.6. PCA High-Speed Output Mode Diagram Rev. 0.2 215 C8051F336/7/8/9 25.3.4. Frequency Output Mode Frequency Output Mode produces a programmable-frequency square wave on the module's associated CEXn pin. The capture/compare module high byte holds the number of PCA clocks to count before the output is toggled. The frequency of the square wave is then defined by Equation 25.1. F PCA F CEXn = ---------------------------------------2 x PCA0CPHn Note: A value of 0x00 in the PCA0CPHn register is equal to 256 for this equation. Equation 25.1. Square Wave Frequency Output Where FPCA is the frequency of the clock selected by the CPS2-0 bits in the PCA mode register, PCA0MD. The lower byte of the capture/compare module is compared to the PCA counter low byte; on a match, CEXn is toggled and the offset held in the high byte is added to the matched value in PCA0CPLn. Frequency Output Mode is enabled by setting the ECOMn, TOGn, and PWMn bits in the PCA0CPMn register. Note that the MATn bit should normally be set to `0' in this mode. If the MATn bit is set to `1', the CCFn flag for the channel will be set when the 16-bit PCA0 counter and the 16-bit capture/compare register for the channel are equal. Write to PCA0CPLn Reset Write to PCA0CPHn 0 ENB PCA0CPMn ENB 1 P ECCMT P E WC A A AOWC MOPP TGMC 1 MP N n n n F 6nnn n n x 000 x Enable PCA0CPLn 8-bit Adder Adder Enable PCA0CPHn TOGn Toggle 8-bit Comparator match 0 CEXn 1 Crossbar Port I/O PCA Timebase PCA0L Figure 25.7. PCA Frequency Output Mode 216 Rev. 0.2 C8051F336/7/8/9 25.3.5. 8-bit, 9-bit, 10-bit and 11-bit Pulse Width Modulator Modes Each module can be used independently to generate a pulse width modulated (PWM) output on its associated CEXn pin. The frequency of the output is dependent on the timebase for the PCA counter/timer, and the setting of the PWM cycle length (8, 9, 10 or 11-bits). For backwards-compatibility with the 8-bit PWM mode available on other devices, the 8-bit PWM mode operates slightly different than 9, 10 and 11-bit PWM modes. It is important to note that all channels configured for 8/9/10/11-bit PWM mode will use the same cycle length. It is not possible to configure one channel for 8-bit PWM mode and another for 11bit mode (for example). However, other PCA channels can be configured to Pin Capture, High-Speed Output, Software Timer, Frequency Output, or 16-bit PWM mode independently. 25.3.5.1. 8-bit Pulse Width Modulator Mode The duty cycle of the PWM output signal in 8-bit PWM mode is varied using the module's PCA0CPLn capture/compare register. When the value in the low byte of the PCA counter/timer (PCA0L) is equal to the value in PCA0CPLn, the output on the CEXn pin will be set. When the count value in PCA0L overflows, the CEXn output will be reset (see Figure 25.8). Also, when the counter/timer low byte (PCA0L) overflows from 0xFF to 0x00, PCA0CPLn is reloaded automatically with the value stored in the module's capture/compare high byte (PCA0CPHn) without software intervention. Setting the ECOMn and PWMn bits in the PCA0CPMn register, and setting the CLSEL bits in register PCA0PWM to 00b enables 8-Bit Pulse Width Modulator mode. If the MATn bit is set to `1', the CCFn flag for the module will be set each time an 8-bit comparator match (rising edge) occurs. The COVF flag in PCA0PWM can be used to detect the overflow (falling edge), which will occur every 256 PCA clock cycles. The duty cycle for 8-Bit PWM Mode is given in Equation 25.2. Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn bit to `0'; writing to PCA0CPHn sets ECOMn to `1'. ( 256 - PCA0CPHn ) Duty Cycle = -------------------------------------------------256 Equation 25.2. 8-Bit PWM Duty Cycle Using Equation 25.2, the largest duty cycle is 100% (PCA0CPHn = 0), and the smallest duty cycle is 0.39% (PCA0CPHn = 0xFF). A 0% duty cycle may be generated by clearing the ECOMn bit to `0'. Rev. 0.2 217 C8051F336/7/8/9 Write to PCA0CPLn Reset Write to PCA0CPHn 0 ENB PCA0CPHn ENB 1 COVF PCA0PWM A R S E L 0 PCA0CPMn C L S E L 0 P ECCMT P E WC A A AOWC MOPP TGMC 1 MPN n n n F 6nnn n n 0 00x0 x Enable CE OC VO FV C L S E L 1 PCA0CPLn x 00 8-bit Comparator match S SET Q CEXn Crossbar Port I/O R PCA Timebase CLR Q PCA0L Overflow Figure 25.8. PCA 8-Bit PWM Mode Diagram 218 Rev. 0.2 C8051F336/7/8/9 25.3.5.2. 9/10/11-bit Pulse Width Modulator Mode The duty cycle of the PWM output signal in 9/10/11-bit PWM mode should be varied by writing to an "AutoReload" Register, which is dual-mapped into the PCA0CPHn and PCA0CPLn register locations. The data written to define the duty cycle should be right-justified in the registers. The auto-reload registers are accessed (read or written) when the bit ARSEL in PCA0PWM is set to `1'. The capture/compare registers are accessed when ARSEL is set to `0'. When the least-significant N bits of the PCA0 counter match the value in the associated module's capture/compare register (PCA0CPn), the output on CEXn is asserted high. When the counter overflows from the Nth bit, CEXn is asserted low (see Figure 1). Upon an overflow from the Nth bit, the COVF flag is set, and the value stored in the module's auto-reload register is loaded into the capture/compare register. The value of N is determined by the CLSEL bits in register PCA0PWM. The 9, 10 or 11-bit PWM mode is selected by setting the ECOMn and PWMn bits in the PCA0CPMn register, and setting the CLSEL bits in register PCA0PWM to the desired cycle length (other than 8-bits). If the MATn bit is set to `1', the CCFn flag for the module will be set each time a comparator match (rising edge) occurs. The COVF flag in PCA0PWM can be used to detect the overflow (falling edge), which will occur every 512 (9-bit), 1024 (10-bit) or 2048 (11-bit) PCA clock cycles. The duty cycle for 9/10/11-Bit PWM Mode is given in Equation 25.2, where N is the number of bits in the PWM cycle. Important Note About PCA0CPHn and PCA0CPLn Registers: When writing a 16-bit value to the PCA0CPn registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn bit to `0'; writing to PCA0CPHn sets ECOMn to `1'. ( 2 N - PCA0CPn ) Duty Cycle = ------------------------------------------2N Equation 25.3. 9, 10, and 11-Bit PWM Duty Cycle A 0% duty cycle may be generated by clearing the ECOMn bit to `0'. Write to PCA0CPLn Reset Write to PCA0CPHn 0 ENB R/W when ARSEL = 1 (Auto-Reload) PCA0CPH:Ln (right-justified) PCA0PWM A R S E L CE OC VO FV C L S E L 1 C L S E L 0 Set "N" bits: 01 = 9 bits 10 = 10 bits 11 = 11 bits ENB 1 PCA0CPMn P ECCMT P E WC A A AOWC MOPP TGMC 1 MP N n n n F 6nnn n n 0 00x0 x Enable R/W when ARSEL = 0 x (Capture/Compare) PCA0CPH:Ln (right-justified) N-bit Comparator match S SET Q CEXn Crossbar Port I/O R PCA Timebase CLR Q PCA0H:L Overflow of Nth Bit Figure 1. PCA 9, 10 and 11-Bit PWM Mode Diagram Rev. 0.2 219 C8051F336/7/8/9 25.3.6. 16-Bit Pulse Width Modulator Mode A PCA module may also be operated in 16-Bit PWM mode. 16-bit PWM mode is independent of the other (8/9/10/11-bit) PWM modes. In this mode, the 16-bit capture/compare module defines the number of PCA clocks for the low time of the PWM signal. When the PCA counter matches the module contents, the output on CEXn is asserted high; when the 16-bit counter overflows, CEXn is asserted low. To output a varying duty cycle, new value writes should be synchronized with PCA CCFn match interrupts. 16-Bit PWM Mode is enabled by setting the ECOMn, PWMn, and PWM16n bits in the PCA0CPMn register. For a varying duty cycle, match interrupts should be enabled (ECCFn = 1 AND MATn = 1) to help synchronize the capture/compare register writes. If the MATn bit is set to `1', the CCFn flag for the module will be set each time a 16-bit comparator match (rising edge) occurs. The CF flag in PCA0CN can be used to detect the overflow (falling edge). The duty cycle for 16-Bit PWM Mode is given by Equation 25.4. Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn bit to `0'; writing to PCA0CPHn sets ECOMn to `1'. ( 65536 - PCA0CPn ) Duty Cycle = ---------------------------------------------------65536 Equation 25.4. 16-Bit PWM Duty Cycle Using Equation 25.4, the largest duty cycle is 100% (PCA0CPn = 0), and the smallest duty cycle is 0.0015% (PCA0CPn = 0xFFFF). A 0% duty cycle may be generated by clearing the ECOMn bit to `0'. Write to PCA0CPLn Reset Write to PCA0CPHn 0 ENB ENB 1 PCA0CPMn P ECCMT P E WC A A AOWC MOPP TGMC 1 MP N n n n F 6nnn n n 1 00x0 x Enable PCA0CPHn PCA0CPLn 16-bit Comparator match S SET Q CEXn Crossbar Port I/O R PCA Timebase CLR Q PCA0H PCA0L Overflow Figure 25.9. PCA 16-Bit PWM Mode 220 Rev. 0.2 C8051F336/7/8/9 25.4. Watchdog Timer Mode A programmable watchdog timer (WDT) function is available through the PCA Module 2. The WDT is used to generate a reset if the time between writes to the WDT update register (PCA0CPH2) exceed a specified limit. The WDT can be configured and enabled/disabled as needed by software. With the WDTE bit set in the PCA0MD register, Module 2 operates as a watchdog timer (WDT). The Module 2 high byte is compared to the PCA counter high byte; the Module 2 low byte holds the offset to be used when WDT updates are performed. The Watchdog Timer is enabled on reset. Writes to some PCA registers are restricted while the Watchdog Timer is enabled. The WDT will generate a reset shortly after code begins execution. To avoid this reset, the WDT should be explicitly disabled (and optionally re-configured and re-enabled if it is used in the system). 25.4.1. Watchdog Timer Operation While the WDT is enabled: * * * * * * PCA counter is forced on. Writes to PCA0L and PCA0H are not allowed. PCA clock source bits (CPS2-CPS0) are frozen. PCA Idle control bit (CIDL) is frozen. Module 2 is forced into software timer mode. Writes to the Module 2 mode register (PCA0CPM2) are disabled. While the WDT is enabled, writes to the CR bit will not change the PCA counter state; the counter will run until the WDT is disabled. The PCA counter run control bit (CR) will read zero if the WDT is enabled but user software has not enabled the PCA counter. If a match occurs between PCA0CPH2 and PCA0H while the WDT is enabled, a reset will be generated. To prevent a WDT reset, the WDT may be updated with a write of any value to PCA0CPH2. Upon a PCA0CPH2 write, PCA0H plus the offset held in PCA0CPL2 is loaded into PCA0CPH2 (See Figure 25.10). PCA0MD CWW I DD DTL LEC K CCCE PPPC SSSF 210 PCA0CPH2 Enable 8-bit Comparator Match Reset PCA0CPL2 8-bit Adder Adder Enable PCA0H PCA0L Overflow Write to PCA0CPH2 Figure 25.10. PCA Module 2 with Watchdog Timer Enabled Rev. 0.2 221 C8051F336/7/8/9 Note that the 8-bit offset held in PCA0CPH2 is compared to the upper byte of the 16-bit PCA counter. This offset value is the number of PCA0L overflows before a reset. Up to 256 PCA clocks may pass before the first PCA0L overflow occurs, depending on the value of the PCA0L when the update is performed. The total offset is then given (in PCA clocks) by Equation 25.5, where PCA0L is the value of the PCA0L register at the time of the update. Offset = ( 256 x PCA0CPL2 ) + ( 256 - PCA0L ) Equation 25.5. Watchdog Timer Offset in PCA Clocks The WDT reset is generated when PCA0L overflows while there is a match between PCA0CPH2 and PCA0H. Software may force a WDT reset by writing a `1' to the CCF2 flag (PCA0CN.2) while the WDT is enabled. 25.4.2. Watchdog Timer Usage To configure the WDT, perform the following tasks: * * * * * * Disable the WDT by writing a `0' to the WDTE bit. Select the desired PCA clock source (with the CPS2-CPS0 bits). Load PCA0CPL2 with the desired WDT update offset value. Configure the PCA Idle mode (set CIDL if the WDT should be suspended while the CPU is in Idle mode). Enable the WDT by setting the WDTE bit to `1'. Reset the WDT timer by writing to PCA0CPH2. The PCA clock source and Idle mode select cannot be changed while the WDT is enabled. The watchdog timer is enabled by setting the WDTE or WDLCK bits in the PCA0MD register. When WDLCK is set, the WDT cannot be disabled until the next system reset. If WDLCK is not set, the WDT is disabled by clearing the WDTE bit. The WDT is enabled following any reset. The PCA0 counter clock defaults to the system clock divided by 12, PCA0L defaults to 0x00, and PCA0CPL2 defaults to 0x00. Using Equation 25.5, this results in a WDT timeout interval of 256 PCA clock cycles, or 3072 system clock cycles. Table 25.3 lists some example timeout intervals for typical system clocks. Table 25.3. Watchdog Timer Timeout Intervals1 System Clock (Hz) 24,500,000 24,500,000 24,500,000 3,062,5002 3,062,5002 3,062,500 32,000 32,000 32,000 2 PCA0CPL2 255 128 32 255 128 32 255 128 32 Timeout Interval (ms) 32.1 16.2 4.1 257 129.5 33.1 24576 12384 3168 Notes: 1. Assumes SYSCLK/12 as the PCA clock source, and a PCA0L value of 0x00 at the update time. 2. Internal SYSCLK reset frequency = Internal Oscillator divided by 8. 222 Rev. 0.2 C8051F336/7/8/9 25.5. Register Descriptions for PCA0 Following are detailed descriptions of the special function registers related to the operation of the PCA. SFR Definition 25.1. PCA0CN: PCA Control Bit Name Type Reset 7 CF R/W 0 6 CR R/W 0 R 0 R 0 R 0 5 4 3 2 CCF2 R/W 0 1 CCF1 R/W 0 0 CCF0 R/W 0 SFR Address = 0xD8; Bit-Addressable Bit Name 7 CF PCA Counter/Timer Overflow Flag. Function Set by hardware when the PCA Counter/Timer overflows from 0xFFFF to 0x0000. When the Counter/Timer Overflow (CF) interrupt is enabled, setting this bit causes the CPU to vector to the PCA interrupt service routine. This bit is not automatically cleared by hardware and must be cleared by software. 6 CR PCA Counter/Timer Run Control. This bit enables/disables the PCA Counter/Timer. 0: PCA Counter/Timer disabled. 1: PCA Counter/Timer enabled. 5:3 2 UNUSED Unused. Read = 000b, Write = Don't care. CCF2 PCA Module 2 Capture/Compare Flag. This bit is set by hardware when a match or capture occurs. When the CCF2 interrupt is enabled, setting this bit causes the CPU to vector to the PCA interrupt service routine. This bit is not automatically cleared by hardware and must be cleared by software. 1 CCF1 PCA Module 1 Capture/Compare Flag. This bit is set by hardware when a match or capture occurs. When the CCF1 interrupt is enabled, setting this bit causes the CPU to vector to the PCA interrupt service routine. This bit is not automatically cleared by hardware and must be cleared by software. 0 CCF0 PCA Module 0 Capture/Compare Flag. This bit is set by hardware when a match or capture occurs. When the CCF0 interrupt is enabled, setting this bit causes the CPU to vector to the PCA interrupt service routine. This bit is not automatically cleared by hardware and must be cleared by software. Rev. 0.2 223 C8051F336/7/8/9 SFR Definition 25.2. PCA0MD: PCA Mode Bit Name Type Reset 7 CIDL R/W 0 6 WDTE R/W 1 5 WDLCK R/W 0 R 0 4 3 CPS2 R/W 0 2 CPS1 R/W 0 1 CPS0 R/W 0 0 ECF R/W 0 SFR Address = 0xD9 Bit Name 7 CIDL PCA Counter/Timer Idle Control. Function Specifies PCA behavior when CPU is in Idle Mode. 0: PCA continues to function normally while the system controller is in Idle Mode. 1: PCA operation is suspended while the system controller is in Idle Mode. 6 WDTE Watchdog Timer Enable If this bit is set, PCA Module 2 is used as the watchdog timer. 0: Watchdog Timer disabled. 1: PCA Module 2 enabled as Watchdog Timer. 5 WDLCK Watchdog Timer Lock This bit locks/unlocks the Watchdog Timer Enable. When WDLCK is set, the Watchdog Timer may not be disabled until the next system reset. 0: Watchdog Timer Enable unlocked. 1: Watchdog Timer Enable locked. 4 3:1 UNUSED Unused. Read = 0b, Write = Don't care. CPS[2:0] PCA Counter/Timer Pulse Select. These bits select the timebase source for the PCA counter 000: System clock divided by 12 001: System clock divided by 4 010: Timer 0 overflow 011: High-to-low transitions on ECI (max rate = system clock divided by 4) 100: System clock 101: External clock divided by 8 (synchronized with the system clock) 11x: Reserved 0 ECF PCA Counter/Timer Overflow Interrupt Enable. This bit sets the masking of the PCA Counter/Timer Overflow (CF) interrupt. 0: Disable the CF interrupt. 1: Enable a PCA Counter/Timer Overflow interrupt request when CF (PCA0CN.7) is set. Note: When the WDTE bit is set to `1', the other bits in the PCA0MD register cannot be modified. To change the contents of the PCA0MD register, the Watchdog Timer must first be disabled. 224 Rev. 0.2 C8051F336/7/8/9 SFR Definition 25.3. PCA0PWM: PCA PWM Configuration Bit Name Type Reset 7 ARSEL R/W 0 6 ECOV R/W 0 5 COVF R/W 0 R 0 R 0 R 0 0 4 3 2 1 0 CLSEL[1:0] R/W 0 SFR Address = 0xF7 Bit Name 7 ARSEL Auto-Reload Register Select. Function This bit selects whether to read and write the normal PCA capture/compare registers (PCA0CPn), or the Auto-Reload registers at the same SFR addresses. This function is used to define the reload value for 9, 10, and 11-bit PWM modes. In all other modes, the Auto-Reload registers have no function. 0: Read/Write Capture/Compare Registers at PCA0CPHn and PCA0CPLn. 1: Read/Write Auto-Reload Registers at PCA0CPHn and PCA0CPLn. 6 ECOV Cycle Overflow Interrupt Enable. This bit sets the masking of the Cycle Overflow Flag (COVF) interrupt. 0: COVF will not generate PCA interrupts. 1: A PCA interrupt will be generated when COVF is set. Cycle Overflow Flag. This bit indicates an overflow of the 8th, 9th, 10th, or 11th bit of the main PCA counter (PCA0). The specific bit used for this flag depends on the setting of the Cycle Length Select bits. The bit can be set by hardware or software, but must be cleared by software. 0: No overflow has occurred since the last time this bit was cleared. 1: An overflow has occurred since the last time this bit was cleared. 4:2 UNUSED Unused. Read = 000b; Write = Don't care. When 16-bit PWM mode is not selected, these bits select the length of the PWM cycle, between 8, 9, 10, or 11 bits. This affects all channels configured for PWM which are not using 16-bit PWM mode. These bits are ignored for individual channels configured to16-bit PWM mode. 00: 8 bits. 01: 9 bits. 10: 10 bits. 11: 11 bits. 5 COVF 1:0 CLSEL[1:0] Cycle Length Select. Rev. 0.2 225 C8051F336/7/8/9 SFR Definition 25.4. PCA0CPMn: PCA Capture/Compare Mode Bit Name Type Reset 7 PWM16n R/W 0 6 ECOMn R/W 0 5 CAPPn R/W 0 4 CAPNn R/W 0 3 MATn R/W 0 2 TOGn R/W 0 1 PWMn R/W 0 0 ECCFn R/W 0 SFR Addresses: PCA0CPM0 = 0xDA, PCA0CPM1 = 0xDB, PCA0CPM2 = 0xDC Bit Name Function 7 PWM16n 16-bit Pulse Width Modulation Enable. This bit enables 16-bit mode when Pulse Width Modulation mode is enabled. 0: 8 to 11-bit PWM selected. 1: 16-bit PWM selected. 6 5 4 3 ECOMn CAPPn CAPNn MATn Comparator Function Enable. This bit enables the comparator function for PCA module n when set to `1'. Capture Positive Function Enable. This bit enables the positive edge capture for PCA module n when set to `1'. Capture Negative Function Enable. This bit enables the negative edge capture for PCA module n when set to `1'. Match Function Enable. This bit enables the match function for PCA module n when set to `1'. When enabled, matches of the PCA counter with a module's capture/compare register cause the CCFn bit in PCA0MD register to be set to logic 1. 2 TOGn Toggle Function Enable. This bit enables the toggle function for PCA module n when set to `1'. When enabled, matches of the PCA counter with a module's capture/compare register cause the logic level on the CEXn pin to toggle. If the PWMn bit is also set to logic 1, the module operates in Frequency Output Mode. 1 PWMn Pulse Width Modulation Mode Enable. This bit enables the PWM function for PCA module n when set to `1'. When enabled, a pulse width modulated signal is output on the CEXn pin. 8 to 11-bit PWM is used if PWM16n is cleared; 16-bit mode is used if PWM16n is set to logic 1. If the TOGn bit is also set, the module operates in Frequency Output Mode. 0 ECCFn Capture/Compare Flag Interrupt Enable. This bit sets the masking of the Capture/Compare Flag (CCFn) interrupt. 0: Disable CCFn interrupts. 1: Enable a Capture/Compare Flag interrupt request when CCFn is set. Note: When the WDTE bit is set to `1', the PCA0CPM2 register cannot be modified, and module 2 acts as the watchdog timer. To change the contents of the PCA0CPM2 register or the function of module 2, the Watchdog Timer must be disabled. 226 Rev. 0.2 C8051F336/7/8/9 SFR Definition 25.5. PCA0L: PCA Counter/Timer Low Byte Bit Name Type Reset R/W 0 R/W 0 R/W 0 7 6 5 4 PCA0[7:0] R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 3 2 1 0 SFR Address = 0xF9 Bit Name 7:0 PCA0[7:0] PCA Counter/Timer Low Byte. Function The PCA0L register holds the low byte (LSB) of the 16-bit PCA Counter/Timer. Note: When the WDTE bit is set to `1', the PCA0L register cannot be modified by software. To change the contents of the PCA0L register, the Watchdog Timer must first be disabled. SFR Definition 25.6. PCA0H: PCA Counter/Timer High Byte Bit Name Type Reset R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 PCA0[15:8] R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 SFR Address = 0xFA Bit Name 7:0 PCA0[15:8] PCA Counter/Timer High Byte. Function The PCA0H register holds the high byte (MSB) of the 16-bit PCA Counter/Timer. Reads of this register will read the contents of a "snapshot" register, whose contents are updated only when the contents of PCA0L are read (see Section 25.1). Note: When the WDTE bit is set to `1', the PCA0H register cannot be modified by software. To change the contents of the PCA0H register, the Watchdog Timer must first be disabled. Rev. 0.2 227 C8051F336/7/8/9 SFR Definition 25.7. PCA0CPLn: PCA Capture Module Low Byte Bit Name Type Reset R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 PCA0CPn[7:0] R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 SFR Addresses: PCA0CPL0 = 0xFB, PCA0CPL1 = 0xE9, PCA0CPL2 = 0xEB Bit Name Function 7:0 PCA0CPn[7:0] PCA Capture Module Low Byte. The PCA0CPLn register holds the low byte (LSB) of the 16-bit capture module n. This register address also allows access to the low byte of the corresponding PCA channel's auto-reload value for 9, 10, or 11-bit PWM mode. The ARSEL bit in register PCA0PWM controls which register is accessed. Note: A write to this register will clear the module's ECOMn bit to a `0'. SFR Definition 25.8. PCA0CPHn: PCA Capture Module High Byte Bit Name Type Reset R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 PCA0CPn[15:8] R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 SFR Addresses: PCA0CPH0 = 0xFC, PCA0CPH1 = 0xEA, PCA0CPH2 = 0xEC Bit Name Function 7:0 PCA0CPn[15:8] PCA Capture Module High Byte. The PCA0CPHn register holds the high byte (MSB) of the 16-bit capture module n. This register address also allows access to the high byte of the corresponding PCA channel's auto-reload value for 9, 10, or 11-bit PWM mode. The ARSEL bit in register PCA0PWM controls which register is accessed. Note: A write to this register will set the module's ECOMn bit to a `1'. 228 Rev. 0.2 C8051F336/7/8/9 26. C2 Interface C8051F336/7/8/9 devices include an on-chip Silicon Labs 2-Wire (C2) debug interface to allow Flash programming and in-system debugging with the production part installed in the end application. The C2 interface uses a clock signal (C2CK) and a bi-directional C2 data signal (C2D) to transfer information between the device and a host system. See the C2 Interface Specification for details on the C2 protocol. 26.1. C2 Interface Registers The following describes the C2 registers necessary to perform Flash programming through the C2 interface. All C2 registers are accessed through the C2 interface as described in the C2 Interface Specification. C2 Register Definition 26.1. C2ADD: C2 Address Bit Name Type Reset 0 0 0 0 7 6 5 4 3 2 1 0 C2ADD[7:0] R/W 0 0 0 0 Bit Name Function The C2ADD register is accessed via the C2 interface to select the target Data register for C2 Data Read and Data Write commands. Address 0x00 0x01 0x02 0xB4 Description Selects the Device ID register for Data Read instructions Selects the Revision ID register for Data Read instructions Selects the C2 Flash Programming Control register for Data Read/Write instructions Selects the C2 Flash Programming Data register for Data Read/Write instructions 7:0 C2ADD[7:0] C2 Address. Rev. 0.2 229 C8051F336/7/8/9 C2 Register Definition 26.2. DEVICEID: C2 Device ID Bit Name Type Reset 0 0 0 1 7 6 5 4 3 2 1 0 DEVICEID[7:0] R/W 0 1 0 0 C2 Address: 0x00 Bit Name 7:0 DEVICEID[7:0] Device ID. Function This read-only register returns the 8-bit device ID: 0x14 (C8051F336/7/8/9). C2 Register Definition 26.3. REVID: C2 Revision ID Bit Name Type Reset Varies Varies Varies Varies 7 6 5 4 3 2 1 0 REVID[7:0] R/W Varies Varies Varies Varies C2 Address: 0x01 Bit Name 7:0 REVID[7:0] Revision ID. Function This read-only register returns the 8-bit revision ID. For example: 0x00 = Revision A. 230 Rev. 0.2 C8051F336/7/8/9 C2 Register Definition 26.4. FPCTL: C2 Flash Programming Control Bit Name Type Reset 0 0 0 0 7 6 5 4 3 2 1 0 FPCTL[7:0] R/W 0 0 0 0 C2 Address: 0x02 Bit Name 7:0 Function This register is used to enable Flash programming via the C2 interface. To enable C2 Flash programming, the following codes must be written in order: 0x02, 0x01. Note that once C2 Flash programming is enabled, a system reset must be issued to resume normal operation. FPCTL[7:0] Flash Programming Control Register. C2 Register Definition 26.5. FPDAT: C2 Flash Programming Data Bit Name Type Reset 0 0 0 0 7 6 5 4 3 2 1 0 FPDAT[7:0] R/W 0 0 0 0 C2 Address: 0xB4 Bit Name 7:0 Function This register is used to pass Flash commands, addresses, and data during C2 Flash accesses. Valid commands are listed below. Code 0x06 0x07 0x08 0x03 Command Flash Block Read Flash Block Write Flash Page Erase Device Erase FPDAT[7:0] C2 Flash Programming Data Register. Rev. 0.2 231 C8051F336/7/8/9 26.2. C2 Pin Sharing The C2 protocol allows the C2 pins to be shared with user functions so that in-system debugging and Flash programming may be performed. This is possible because C2 communication is typically performed when the device is in the halt state, where all on-chip peripherals and user software are stalled. In this halted state, the C2 interface can safely `borrow' the C2CK (RST) and C2D pins. In most applications, external resistors are required to isolate C2 interface traffic from the user application. A typical isolation configuration is shown in Figure 26.1. C8051Fxxx /Reset (a) Input (b) Output (c) C2CK C2D C2 Interface Master Figure 26.1. Typical C2 Pin Sharing The configuration in Figure 26.1 assumes the following: 1. The user input (b) cannot change state while the target device is halted. 2. The RST pin on the target device is used as an input only. Additional resistors may be necessary depending on the specific application. 232 Rev. 0.2 C8051F336/7/8/9 NOTES: Rev. 0.2 233 C8051F336/7/8/9 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: MCUinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders 234 Rev. 0.2 |
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